control.vhd

自己刚写的一个RISC的cpu

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;

entity control is
       port(clk        :in std_logic;
            rst        :in std_logic;
            instr      :in std_logic_vector(15 downto 0);    
            re         :out std_logic;                      
            wr         :out std_logic;                      
            muxalu1_c  :out std_logic;                       
            muxalu2_c  :out std_logic;                       
            alu_c      :out std_logic_vector(1 downto 0);    
            muxwrd_c   :out std_logic_vector(1 downto 0);    
            en_ir      :out std_logic;                       
            en_wr      :out std_logic;                       
            en_r1      :out std_logic;                       
            en_r2      :out std_logic;                       
            wra        :out std_logic_vector(1 downto 0);   
            rra1       :out std_logic_vector(1 downto 0);    
            rra2       :out std_logic_vector(1 downto 0);   
            comp_c     :out std_logic_vector(2 downto 0);    
            pcalu_c    :out std_logic_vector(2 downto 0);    
            jmp_imm    :out std_logic_vector(11 downto 0);   
            comp_imm   :out std_logic_vector(7 downto 0);    
            rdm_imm    :out std_logic_vector(9 downto 0);    
            muxwrd_mov :out std_logic                        
            );
end entity control;

architecture one of control is
       subtype state_type is std_logic_vector(1 downto 0);
       constant FETCH    :state_type:="00";
       constant DECODE   :state_type:="01";
       constant EXECUTE  :state_type:="10";
       
       signal cur_state  :state_type;
       signal next_state :state_type;
       
begin
    state_comb:process(cur_state,rst)
                 begin
                   if(rst='1') then
                      next_state<=FETCH;
                   else
                    CASE cur_state is
                      WHEN FETCH=>
                           next_state<=DECODE;
                      WHEN DECODE=>
                           next_state<=EXECUTE;
                      WHEN OTHERS=>
                           next_state<=FETCH;
                     end case;
                   end if;
               end process state_comb;
                                
    state_sync:process(rst,clk)
                 begin
                   if (rst='1') then
                      cur_state<=FETCH;
                   ELSIF(rising_edge(clk)) then
                      cur_state<=next_state;
                   end if;
               end process state_sync;
                  
     BODY_MAIN:PROCESS(cur_state,instr,rst)
                  variable rs,rt,rd :std_logic_vector(1 downto 0);
                  variable temp:std_logic_vector(3 downto 0);
                  --- variable jmp_imm  :std_logic_vector(11 downto 0);
                  ---variable rdm_imm  :std_logic_vector(9 downto 0);
                  ---variable comp_imm :std_logic_vector(7 downto 0);
              begin
                  rs      :=instr(11 downto 10);
                  rt      :=instr(9 downto 8);
                  rd      :=instr(7 downto 6);
                  temp    :=instr(15 downto 12);
                  ----jmp_imm :=instr(11 downto 0);
                  ----rdm_imm :=instr(9 downto 0);
                  ----comp_imm:=instr(7 downto 0);
                  
                
                  if (rst='1') then
                     re         <='0';
                     wr         <='0';
                     muxalu1_c  <='0';                   
                     muxalu2_c  <='0';                      
                     alu_c      <="00";    
                     muxwrd_c   <="00";
                     en_ir      <='0';
                     en_wr      <='0';
                     en_r1      <='0';
                     en_r2      <='0';                      
                     --wra        <="00";
                     rra1       <="00";
                     rra2       <="00";
                     comp_c     <="000";                      
                     pcalu_c    <=(others=>'0');                     
                     jmp_imm    <=(others=>'0');
                     comp_imm   <=(others=>'0');
                     rdm_imm    <=(others=>'0');
                     muxwrd_mov <='0' ;

                   else
                   -- re<='0';
                    --en_ir<='0';
                    
                  case cur_state is
                  
                      when FETCH =>
                          re<='1';
                          en_ir<='1';
                          wr<='0';
                          muxalu1_c<='0';                   
                          muxalu2_c<='0';                      
                          alu_c<="00";    
                          muxwrd_c<="11";
                          en_wr<='0';
                          en_r1<='0';
                          en_r2<='0';                      
                          --wra<="00";
                          rra1<="00";
                          rra2<="00";
                          comp_c<="000";                      
                          pcalu_c<=(others=>'0');                     
                          jmp_imm<=(others=>'0');
                          comp_imm<=(others=>'0');
                          rdm_imm<=(others=>'0');
                          muxwrd_mov<='0' ;
                          
                      when DECODE =>
                           case temp is
                           when "0001"=>
                          --IF((instr(15 downto 12)="0001")or (instr(15 downto 12)="0010")
                           --      or(instr(15 downto 12)="0011")) then
                           -----and,or,xor
                           alu_c<=instr(13 downto 12);
                           rra1<=instr(11 downto 10);
                           en_r1<='1';
                           rra2<=instr(9 downto 8);
                           en_r2<='1';
                           --en_wr<='0';
                           en_ir<='0';
                           en_wr<='0';
                           re<='0';
                           wra<=instr(7 downto 6);
                           muxalu1_c<='1';
                           muxalu2_c<='1';
                           muxwrd_c<="11";
                           pcalu_c<="100" ;

                           when "0010"=>
                          --IF((instr(15 downto 12)="0001")or (instr(15 downto 12)="0010")
                           --      or(instr(15 downto 12)="0011")) then
                           -----and,or,xor
                           alu_c<=instr(13 downto 12);
                           rra1<=instr(11 downto 10);
                           en_r1<='1';
                           rra2<=instr(9 downto 8);
                           en_r2<='1';
                           --en_wr<='0';
                           en_ir<='0';
                           en_wr<='0';
                           re<='0';
                           wra<=instr(7 downto 6);
                           muxalu1_c<='1';
                           muxalu2_c<='1';
                           muxwrd_c<="11";
                           pcalu_c<="100" ;
                           
                           --end if;
                           when "0011"=>
                          --IF((instr(15 downto 12)="0001")or (instr(15 downto 12)="0010")
                           --      or(instr(15 downto 12)="0011")) then
                           -----and,or,xor
                           alu_c<=instr(13 downto 12);
                           rra1<=instr(11 downto 10);
                           en_r1<='1';
                           rra2<=instr(9 downto 8);
                           en_r2<='1';
                           en_wr<='0';
                           en_ir<='0';
                           re<='0';
                           wra<=instr(7 downto 6);
                           muxalu1_c<='1';
                           muxalu2_c<='1';
                           muxwrd_c<="11";
                           pcalu_c<="100" ;
                           
                           --end if;
                           
                            when "0100"=>
                         -- if(instr(15 downto 12)="0100") then
                            ----mov
                            re<='0';
                            en_ir<='0';
                            en_r1<='0';
                            en_r2<='0';   
                            en_wr<='1';
                            wra<=rs;
                            muxwrd_c<="01";
                            muxwrd_mov<=instr(0);
                            pcalu_c<="100" ;
                            --end if;
                           
                           when "0101" =>
                          --if(instr(15 downto 12)="0101") then
                             ----jmp
                             pcalu_c<="010";
                             en_ir<='0';
                             re<='0';
                             muxalu1_c<='0';