ram.vhd

来自「自己刚写的一个RISC的cpu」· VHDL 代码 · 共 38 行

library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;


entity ram is
       port(address:in std_logic_vector(15 downto 0);
            ram_out:out std_logic;
            clk:in std_logic;
            re:in std_logic;
            wr:in std_logic
            );
end entity ram;

architecture one of ram is
       type array2 is array (0 to 255) of std_logic;
       signal regf:array2:=(
                            '1',
                            '0',
                            '1',
                            '1',
                            '0',
                            '1',others=>'0'
                            );  
       begin
      process(clk)
      begin
       if (clk'event and clk='1') then
          if(re='1') then
            ram_out<=regf(to_integer(unsigned(address)));
          else  
            ram_out<='0';
         end if;
         end if;   
       end process;                                   
end one;