muxwrd.vhd

自己刚写的一个RISC的cpu

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith;
use ieee.std_logic_unsigned.all;

entity muxwrd is
       port(muxwrd_c:in std_logic_vector(1 downto 0);
            muxwrd_alu:in std_logic;
            muxwrd_mov:in std_logic;
            muxwrd_rdm:in std_logic;
            muxwrd_out:out std_logic
            );
end muxwrd;

architecture one of muxwrd is
  begin
    process(muxwrd_alu,muxwrd_mov,muxwrd_rdm,muxwrd_c)
    begin
      case muxwrd_c is
          when "00"=>
                muxwrd_out<=muxwrd_alu;
          when "01"=>
                muxwrd_out<=muxwrd_mov;
          when "10"=>
                muxwrd_out<=muxwrd_rdm; 
          when others=>
                null;
      end case;
    end process;
 end one;