regfile.vhd

自己刚写的一个RISC的cpu

library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith;
use ieee.std_logic_unsigned.all;
--use ieee.numeric_std.all;

entity regfile is
       port( clk:in std_logic;
             reset:in std_logic;
             en_wr:in std_logic;
             en_r1:in std_logic;
             en_r2:in std_logic;
             wra:in std_logic_vector(1 downto 0);
             wrd:in std_logic;
             rra1:in std_logic_vector(1 downto 0);
             rra2:in std_logic_vector(1 downto 0);
             rsd:out std_logic;
             rtd:out std_logic
             );
end regfile;

architecture one of regfile is
     signal regf:std_logic_vector(3 downto 0):=(others=>'0');
begin
      process(reset,en_r1,en_r2,wra,clk)
      begin
      if(reset='1') then
       regf<=(others=>'0');
      else
      
        if(en_r1='1') then
            rsd<=regf(conv_integer(rra1));
            else
            rsd<='0';
         end if;
       
         if(en_r2='1') then
            rtd<=regf(conv_integer(rra2));
            else
            rtd<='0';
         end if;
       
          if(rising_edge(clk) and en_wr='1') then
            regf(conv_integer(wra))<=wrd;
         end if;
       end if;
end process;
end one;