autoseller.rpt

自动售饮料机。用vhdl变写的自动售物品的程序。

  _X016  = EXP(!_LC122 &  line3);
  _X017  = EXP(!_LC122 & !line1);
  _EQ030 = !_LC112 & !_LC118 &  _X015 &  _X016 &  _X017;
  _X015  = EXP(!_LC122 &  line2);
  _X016  = EXP(!_LC122 &  line3);
  _X017  = EXP(!_LC122 & !line1);

-- Node name is '~6473~2' 
-- Equation name is '~6473~2', location is LC118, type is buried.
-- synthesized logic cell 
_LC118   = LCELL( _EQ031 $  GND);
  _EQ031 =  fivecoins & !halfcoin &  line1 & !line2 & !line3 & !onecoin & 
             !present_state2
         # !halfcoin & !line0 &  line1 & !line2 & !line3 & !onecoin & 
              present_state1
         # !halfcoin &  line1 & !line2 & !line3 & !onecoin & !present_state2 & 
             !tencoins
         #  halfcoin &  line1 & !line2 & !line3 & !present_state0 & 
             !present_state2
         #  line1 & !line2 & !line3 &  onecoin & !present_state1 & 
             !present_state2;

-- Node name is '~6473~3' 
-- Equation name is '~6473~3', location is LC112, type is buried.
-- synthesized logic cell 
_LC112   = LCELL( _EQ032 $  GND);
  _EQ032 =  line1 & !line2 & !line3 &  present_state0 &  present_state1 & 
              present_state2
         # !line0 &  line1 & !line2 & !line3 &  present_state0 & 
              present_state2
         #  line1 & !line2 & !line3 &  present_state0 & !present_state1 & 
             !present_state2
         #  line1 & !line2 & !line3 &  present_state3
         #  line1 & !line2 & !line3 &  present_state4;

-- Node name is '~6476~1' 
-- Equation name is '~6476~1', location is LC122, type is buried.
-- synthesized logic cell 
_LC122   = LCELL( _EQ033 $  GND);
  _EQ033 = !fivecoins & !halfcoin &  line0 & !line1 & !line2 & !line3 & 
             !onecoin & !present_state0 & !present_state1 & !present_state2 & 
             !present_state3 & !present_state4 &  tencoins
         # !halfcoin &  line0 & !line1 & !line2 & !line3 &  onecoin & 
             !present_state0 &  present_state1 & !present_state2 & 
             !present_state3 & !present_state4
         #  _LC082 &  _X001;
  _X001  = EXP( line0 & !line1 & !line2 & !line3);

-- Node name is '~6485~1' 
-- Equation name is '~6485~1', location is LC088, type is buried.
-- synthesized logic cell 
_LC088   = LCELL( _EQ034 $  _EQ035);
  _EQ034 =  halfcoin & !_LC090 & !_LC112 &  line1 & !line2 & !line3 & 
             !present_state0 & !present_state1 &  present_state2 &  _X018
         # !fivecoins & !halfcoin & !_LC090 & !_LC112 &  line1 & !line2 & 
             !line3 &  present_state1 &  tencoins &  _X018
         #  fivecoins & !halfcoin & !_LC090 & !_LC112 &  line1 & !line2 & 
             !line3 & !onecoin & !present_state1 &  _X018
         # !halfcoin & !_LC090 & !_LC112 &  line1 & !line2 & !line3 & 
             !onecoin & !present_state1 & !tencoins &  _X018;
  _X018  = EXP(!_LC084 & !line1);
  _EQ035 = !_LC090 & !_LC112 &  _X018;
  _X018  = EXP(!_LC084 & !line1);

-- Node name is '~6485~2' 
-- Equation name is '~6485~2', location is LC090, type is buried.
-- synthesized logic cell 
_LC090   = LCELL( _EQ036 $  GND);
  _EQ036 =  halfcoin &  line1 & !line2 & !line3 &  present_state0 & 
             !present_state2
         # !halfcoin &  line1 & !line2 & !line3 &  onecoin &  present_state1
         # !line0 &  line1 & !line2 & !line3 &  present_state1 & 
              present_state2
         # !_LC084 &  line2
         # !_LC084 &  line3;

-- Node name is '~6488~1' 
-- Equation name is '~6488~1', location is LC084, type is buried.
-- synthesized logic cell 
_LC084   = LCELL( _EQ037 $  GND);
  _EQ037 =  _LC095 &  line0 & !line1 & !line2 & !line3
         #  _LC088 &  _X001;
  _X001  = EXP( line0 & !line1 & !line2 & !line3);

-- Node name is '~6497~1' 
-- Equation name is '~6497~1', location is LC121, type is buried.
-- synthesized logic cell 
_LC121   = LCELL( _EQ038 $  _EQ039);
  _EQ038 = !fivecoins & !halfcoin &  line0 &  line1 & !line2 & !line3 & 
             !onecoin & !present_state0 & !present_state3 & !present_state4 & 
             !tencoins
         # !halfcoin &  line1 & !line2 & !line3 & !present_state0 & 
              present_state2 & !present_state3 & !present_state4 &  _X019
         # !halfcoin &  line1 & !line2 & !line3 & !present_state0 & 
              present_state1 & !present_state2 & !present_state3 & 
             !present_state4
         # !_LC125 &  _X010;
  _X019  = EXP(!line0 &  present_state1);
  _X010  = EXP( line1 & !line2 & !line3);
  _EQ039 = !_LC089 & !_LC123 &  _X020 &  _X021;
  _X020  = EXP(!line0 &  line1 & !line2 & !line3 &  present_state3 & 
              present_state4);
  _X021  = EXP(!line0 &  line1 & !line2 & !line3 &  present_state2 & 
              present_state4);

-- Node name is '~6497~2' 
-- Equation name is '~6497~2', location is LC123, type is buried.
-- synthesized logic cell 
_LC123   = LCELL( _EQ040 $  GND);
  _EQ040 =  line1 & !line2 & !line3 &  present_state0 & !present_state1 & 
             !present_state2 & !present_state3 & !present_state4
         # !fivecoins & !line0 &  line1 & !line2 & !line3 & !onecoin & 
             !present_state0 & !present_state1 & !present_state2 & 
             !present_state4 & !tencoins
         #  halfcoin &  line0 &  line1 & !line2 & !line3 &  present_state0 & 
             !present_state1 & !present_state3 & !present_state4
         # !line0 &  line1 & !line2 & !line3 &  present_state0 & 
              present_state1 &  present_state2 & !present_state3
         # !line0 &  line1 & !line2 & !line3 &  present_state0 & 
             !present_state1 &  present_state2 &  present_state3;

-- Node name is '~6497~3' 
-- Equation name is '~6497~3', location is LC089, type is buried.
-- synthesized logic cell 
_LC089   = LCELL( _EQ041 $  GND);
  _EQ041 = !line0 &  line1 & !line2 & !line3 & !present_state0 & 
              present_state1 &  present_state2 &  present_state3
         #  halfcoin &  line1 & !line2 & !line3 &  present_state0 & 
             !present_state2 & !present_state3 & !present_state4
         #  halfcoin &  line1 & !line2 & !line3 & !present_state1 & 
             !present_state2 & !present_state3 & !present_state4
         # !line0 &  line1 & !line2 & !line3 & !present_state0 & 
             !present_state1 & !present_state2 &  present_state3
         # !line0 &  line1 & !line2 & !line3 &  present_state0 & 
              present_state1 &  present_state4;

-- Node name is '~6500~1' 
-- Equation name is '~6500~1', location is LC125, type is buried.
-- synthesized logic cell 
_LC125   = LCELL( _EQ042 $  _EQ043);
  _EQ042 = !fivecoins & !halfcoin & !_LC102 & !_LC106 &  line0 & !line1 & 
             !line2 & !line3 & !onecoin & !present_state0 & !present_state2 & 
             !present_state3 & !present_state4 & !tencoins
         #  halfcoin & !_LC102 & !_LC106 &  line0 & !line1 & !line2 & !line3 & 
             !present_state0 & !present_state1 & !present_state2 & 
             !present_state4
         # !_LC102 & !_LC106 &  line0 & !line1 & !line2 & !line3 & 
              present_state0 &  present_state1 & !present_state2 & 
              present_state3
         # !halfcoin & !_LC102 & !_LC106 &  line0 & !line1 & !line2 & !line3 & 
             !present_state0 &  present_state1 & !present_state3;
  _EQ043 = !_LC102 & !_LC106;

-- Node name is '~6500~2' 
-- Equation name is '~6500~2', location is LC102, type is buried.
-- synthesized logic cell 
_LC102   = LCELL( _EQ044 $  GND);
  _EQ044 = !_LC091 & !_LC121
         #  line0 & !line1 & !line2 & !line3 &  present_state0 & 
             !present_state1 &  present_state2
         #  line0 & !line1 & !line2 & !line3 &  present_state0 & 
              present_state2 & !present_state3
         #  line0 & !line1 & !line2 & !line3 & !present_state0 & 
              present_state1 &  present_state2
         #  line0 & !line1 & !line2 & !line3 &  present_state0 & 
             !present_state1 & !present_state3;

-- Node name is '~6500~3' 
-- Equation name is '~6500~3', location is LC106, type is buried.
-- synthesized logic cell 
_LC106   = LCELL( _EQ045 $  GND);
  _EQ045 =  line0 & !line1 & !line2 & !line3 & !present_state0 & 
             !present_state1 &  present_state3
         #  line0 & !line1 & !line2 & !line3 &  present_state0 & 
              present_state4
         #  line0 & !line1 & !line2 & !line3 &  present_state1 & 
              present_state4
         #  line0 & !line1 & !line2 & !line3 &  present_state2 & 
              present_state4;



--     Shareable expanders that are duplicated in multiple LABs:
--    _X001 occurs in LABs F, G, H




Project Information          f:\my projects\eda-vhdl\autoseller\autoseller.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000A' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 7,449K