📄 autoseller.rpt
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(61) 94 F SOFT s t 4 0 0 6 6 0 2 ~6461~1
(80) 126 H SOFT s t 1 0 1 8 5 0 1 ~6461~2
(76) 120 H LCELL s t 1 1 0 8 6 0 1 ~6464~1
- 82 F SOFT s t 4 0 1 8 6 0 2 ~6473~1
(75) 118 H SOFT s t 1 0 1 8 3 0 1 ~6473~2
(71) 112 G SOFT s t 1 0 1 4 5 0 2 ~6473~3
- 122 H LCELL s t 1 1 0 8 6 0 1 ~6476~1
(57) 88 F SOFT s t 2 0 1 7 6 0 2 ~6485~1
- 90 F SOFT s t 1 0 1 6 4 0 1 ~6485~2
- 84 F LCELL s t 1 1 0 4 2 0 2 ~6488~1
- 121 H SOFT s t 5 1 1 8 8 0 2 ~6497~1
(77) 123 H SOFT s t 1 0 1 8 5 0 1 ~6497~2
- 89 F SOFT s t 1 0 1 5 5 0 1 ~6497~3
(79) 125 H LCELL s t 1 0 1 8 7 0 1 ~6500~1
- 102 G SOFT s t 1 0 1 4 6 0 1 ~6500~2
- 106 G SOFT s t 0 0 0 4 5 0 1 ~6500~3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: f:\my projects\eda-vhdl\autoseller\autoseller.rpt
autoseller
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+----------------------- LC86 coin
| +--------------------- LC83 SOUT2
| | +------------------- LC85 SOUT3
| | | +----------------- LC81 present_state1
| | | | +--------------- LC95 ~2686~1
| | | | | +------------- LC91 ~6403~1
| | | | | | +----------- LC94 ~6461~1
| | | | | | | +--------- LC82 ~6473~1
| | | | | | | | +------- LC88 ~6485~1
| | | | | | | | | +----- LC90 ~6485~2
| | | | | | | | | | +--- LC84 ~6488~1
| | | | | | | | | | | +- LC89 ~6497~3
| | | | | | | | | | | |
| | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | that feed LAB 'F'
LC | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'F':
LC81 -> * - - - * - * * * * - * | - - - - - * * * | <-- present_state1
LC95 -> - - - * - - - - - - * - | - - - - - * - - | <-- ~2686~1
LC88 -> - - - * - - - - - - * - | - - - - - * - - | <-- ~6485~1
LC90 -> - - - - - - - - * - - - | - - - - - * - - | <-- ~6485~2
LC84 -> - - - - - - - - * * - - | - - - - - * - - | <-- ~6488~1
Pin
83 -> - - - - - - - - - - - - | - - - - - - - - | <-- clock
4 -> - - - - * - * * * - - - | - - - - - * - * | <-- fivecoins
5 -> - - - - * - * * * * - * | - - - - - * - * | <-- halfcoin
10 -> * - - * - * - * - * * * | - - - - - * * * | <-- line0
11 -> * - - * - * * * * * * * | - - - - - * * * | <-- line1
12 -> * - - * - * * * * * * * | - - - - - * * * | <-- line2
8 -> * - - * - * * * * * * * | - - - - - * * * | <-- line3
6 -> - - - - * - * * * * - - | - - - - - * - * | <-- onecoin
9 -> - - - * - - - - - - - - | - - - - - * * * | <-- reset
21 -> - - - - * - - * * - - - | - - - - - * - * | <-- tencoins
LC116-> * - - - * - * - - - - * | - - - - - * * * | <-- present_state4
LC114-> * - - - * - * - - - - * | - - - - - * * * | <-- present_state3
LC113-> * - - - * - - * * * - * | - - - - - * * * | <-- present_state2
LC98 -> * - - - * - * * * * - * | - - - - - * * * | <-- present_state0
LC126-> - - - - - - * - - - - - | - - - - - * - - | <-- ~6461~2
LC120-> - - - - - - * - - - - - | - - - - - * - - | <-- ~6464~1
LC118-> - - - - - - - * - - - - | - - - - - * - - | <-- ~6473~2
LC112-> - - - - - - - * * - - - | - - - - - * - - | <-- ~6473~3
LC122-> - - - - - - - * - - - - | - - - - - * - - | <-- ~6476~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\my projects\eda-vhdl\autoseller\autoseller.rpt
autoseller
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+--------------------------- LC97 ret
| +------------------------- LC101 SOUT0
| | +----------------------- LC105 SOUT1
| | | +--------------------- LC109 SOUT4
| | | | +------------------- LC107 SOUT5
| | | | | +----------------- LC99 SOUT6
| | | | | | +--------------- LC104 SOUT7
| | | | | | | +------------- LC98 present_state0
| | | | | | | | +----------- LC100 ~2749~2
| | | | | | | | | +--------- LC103 ~6404~1
| | | | | | | | | | +------- LC108 ~6404~2
| | | | | | | | | | | +----- LC112 ~6473~3
| | | | | | | | | | | | +--- LC102 ~6500~2
| | | | | | | | | | | | | +- LC106 ~6500~3
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'G'
LC | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
LC98 -> * - - - - - - - * * * * * * | - - - - - * * * | <-- present_state0
LC103-> * - - - - - - - - - - - - - | - - - - - - * - | <-- ~6404~1
LC108-> * - - - - - - - - - - - - - | - - - - - - * - | <-- ~6404~2
Pin
83 -> - - - - - - - - - - - - - - | - - - - - - - - | <-- clock
10 -> * * * * * * * * - * * * * * | - - - - - * * * | <-- line0
11 -> * * * * * * * * - * * * * * | - - - - - * * * | <-- line1
12 -> * * * * * * * * - * * * * * | - - - - - * * * | <-- line2
8 -> * * * * * * * * - * * * * * | - - - - - * * * | <-- line3
9 -> - - - - - - - * - - - - - - | - - - - - * * * | <-- reset
17 -> - * - * * * * - - - - - - - | - - - - - - * - | <-- row0
16 -> - - * * * * * - - - - - - - | - - - - - - * - | <-- row1
18 -> - * * * * * * - - - - - - - | - - - - - - * - | <-- row2
20 -> - * * * * * * - - - - - - - | - - - - - - * - | <-- row3
LC116-> * - - - - - - - - * * * - * | - - - - - * * * | <-- present_state4
LC114-> * - - - - - - - * * * * * * | - - - - - * * * | <-- present_state3
LC113-> * - - - - - - - * * * * * * | - - - - - * * * | <-- present_state2
LC81 -> * - - - - - - - * * * * * * | - - - - - * * * | <-- present_state1
LC124-> - - - - - - - * - - - - - - | - - - - - - * - | <-- ~2749~1
LC91 -> - - - - - - - - - - - - * - | - - - - - - * - | <-- ~6403~1
LC121-> - - - - - - - * - - - - * - | - - - - - - * - | <-- ~6497~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\my projects\eda-vhdl\autoseller\autoseller.rpt
autoseller
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+------------------------------- LC117 dispense
| +----------------------------- LC115 ready
| | +--------------------------- LC116 present_state4
| | | +------------------------- LC114 present_state3
| | | | +----------------------- LC113 present_state2
| | | | | +--------------------- LC124 ~2749~1
| | | | | | +------------------- LC127 ~6449~1
| | | | | | | +----------------- LC128 ~6452~1~2
| | | | | | | | +--------------- LC119 ~6452~1
| | | | | | | | | +------------- LC126 ~6461~2
| | | | | | | | | | +----------- LC120 ~6464~1
| | | | | | | | | | | +--------- LC118 ~6473~2
| | | | | | | | | | | | +------- LC122 ~6476~1
| | | | | | | | | | | | | +----- LC121 ~6497~1
| | | | | | | | | | | | | | +--- LC123 ~6497~2
| | | | | | | | | | | | | | | +- LC125 ~6500~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC116-> * * * * * * * * * * * - * * * * | - - - - - * * * | <-- present_state4
LC114-> * * * * * * * * * * * - * * * * | - - - - - * * * | <-- present_state3
LC113-> * * * * * * * * * * * * * * * * | - - - - - * * * | <-- present_state2
LC127-> - - * - - - - - - - - - - - - - | - - - - - - - * | <-- ~6449~1
LC128-> - - - - - - - - * - - - - - - - | - - - - - - - * | <-- ~6452~1~2
LC119-> - - - - - - * * - - - - - - - - | - - - - - - - * | <-- ~6452~1
LC123-> - - - - - - - - - - - - - * - - | - - - - - - - * | <-- ~6497~2
LC125-> - - - - - - - - - - - - - * - - | - - - - - - - * | <-- ~6500~1
Pin
83 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clock
4 -> - - * * * * * * * * * * * * * * | - - - - - * - * | <-- fivecoins
5 -> - - * * * * * * * * * * * * * * | - - - - - * - * | <-- halfcoin
10 -> * * * * * - * * * * * * * * * * | - - - - - * * * | <-- line0
11 -> * * * * * - * * * * * * * * * * | - - - - - * * * | <-- line1
12 -> * * * * * - * * * * * * * * * * | - - - - - * * * | <-- line2
8 -> * * * * * - * * * * * * * * * * | - - - - - * * * | <-- line3
6 -> - - * * * * * * * * * * * * * * | - - - - - * - * | <-- onecoin
9 -> - - * * * - - - - - - - - - - - | - - - - - * * * | <-- reset
21 -> - - * * * * * * * * * * * * * * | - - - - - * - * | <-- tencoins
LC81 -> * * * * * * * * * * * * * * * * | - - - - - * * * | <-- present_state1
LC98 -> * * * * * * * * * * * * * * * * | - - - - - * * * | <-- present_state0
LC100-> - - - - - * - - - - - - - - - - | - - - - - - - * | <-- ~2749~2
LC94 -> - - - * - - - - - - * - - - - - | - - - - - - - * | <-- ~6461~1
LC82 -> - - - - * - - - - - - - * - - - | - - - - - - - * | <-- ~6473~1
LC89 -> - - - - - - - - - - - - - * - - | - - - - - - - * | <-- ~6497~3
LC102-> - - - - - - - - - - - - - - - * | - - - - - - - * | <-- ~6500~2
LC106-> - - - - - - - - - - - - - - - * | - - - - - - - * | <-- ~6500~3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\my projects\eda-vhdl\autoseller\autoseller.rpt
autoseller
** EQUATIONS **
clock : INPUT;
fivecoins : INPUT;
halfcoin : INPUT;
line0 : INPUT;
line1 : INPUT;
line2 : INPUT;
line3 : INPUT;
onecoin : INPUT;
reset : INPUT;
row0 : INPUT;
row1 : INPUT;
row2 : INPUT;
row3 : INPUT;
tencoins : INPUT;
-- Node name is 'coin'
-- Equation name is 'coin', location is LC086, type is output.
coin = LCELL( _EQ001 $ GND);
_EQ001 = line0 & line1 & !line2 & !line3 & !present_state1 &
present_state2 & !present_state3 & !present_state4
# line0 & line1 & !line2 & !line3 & !present_state0 &
present_state2 & !present_state3 & !present_state4
# line1 & !line2 & !line3 & !present_state0 & !present_state1 &
present_state2 & !present_state3 & !present_state4
# line0 & !line2 & !line3 & !present_state0 & present_state1 &
!present_state2 & !present_state3 & !present_state4
# line1 & !line2 & !line3 & present_state1 & !present_state2 &
!present_state3 & !present_state4;
-- Node name is 'dispense'
-- Equation name is 'dispense', location is LC117, type is output.
dispense = LCELL( _EQ002 $ GND);
_EQ002 = line1 & !line2 & !line3 & present_state0 & !present_state1 &
!present_state2 & !present_state3 & !present_state4
# line0 & !line2 & !line3 & present_state0 & !present_state1 &
!present_state2 & !present_state3 & !present_state4;
-- Node name is ':31' = 'present_state0'
-- Equation name is 'present_state0', location is LC098, type is buried.
present_state0 = DFFE( _EQ003 $ GND, GLOBAL( clock), !reset, VCC, VCC);
_EQ003 = _LC124 & line0 & !line1 & !line2 & !line3
# _LC121 & _X001;
_X001 = EXP( line0 & !line1 & !line2 & !line3);
-- Node name is ':30' = 'present_state1'
-- Equation name is 'present_state1', location is LC081, type is buried.
present_state1 = DFFE( _EQ004 $ GND, GLOBAL( clock), !reset, VCC, VCC);
_EQ004 = _LC095 & line0 & !line1 & !line2 & !line3
# _LC088 & _X001;
_X001 = EXP( line0 & !line1 & !line2 & !line3);
-- Node name is ':29' = 'present_state2'
-- Equation name is 'present_state2', location is LC113, type is buried.
present_state2 = DFFE( _EQ005 $ GND, GLOBAL( clock), !reset, VCC, VCC);
_EQ005 = !fivecoins & !halfcoin & line0 & !line1 & !line2 & !line3 &
!onecoin & !present_state0 & !present_state1 & !present_state2 &
!present_state3 & !present_state4 & tencoins
# !halfcoin & line0 & !line1 & !line2 & !line3 & onecoin &
!present_state0 & present_state1 & !present_state2 &
!present_state3 & !present_state4
# _LC082 & _X001;
_X001 = EXP( line0 & !line1 & !line2 & !line3);
-- Node name is ':28' = 'present_state3'
-- Equation name is 'present_state3', location is LC114, type is buried.
present_state3 = DFFE( _EQ006 $ GND, GLOBAL( clock), !reset, VCC, VCC);
_EQ006 = !halfcoin & line0 & !line1 & !line2 & !line3 & !onecoin &
!present_state0 & !present_state1 & !present_state2 &
!present_state3 & !present_state4 & tencoins
# fivecoins & !halfcoin & line0 & !line1 & !line2 & !line3 &
!onecoin & !present_state0 & !present_state2 & !present_state3 &
!present_state4
# _LC094 & _X001;
_X001 = EXP( line0 & !line1 & !line2 & !line3);
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