lbuff_mem..vhd

延时代码,可以用在ＦＰＧＡ数据流水处理

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--
-- Filename - lbuff_mem.vhd
-- Author - P. Szanto
-- Creation - 27 June 2006
--
-- Description -
--
-- BlockRAM template for the line buffer
-- One write and one read port
-- For Virtex4 and Virtex5 the additional output register is used
--
--
-- $RCSfile: lbuff_mem.vhd,v $ $Revision: 1.7 $ $Date: 2006/06/30 19:01:22 $
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--library work;
use work.rank2d_utils.ALL;

entity lbuff_mem is
generic(DWF       : integer := 24;
        LW_MAX    : integer := 1024;
        FAMILY    : string := "virtex4"
);
port   (clk       : in  std_logic;
        rst       : in  std_logic;
        en        : in  std_logic;
        wr_en     : in  std_logic;
        addr_rd   : in  std_logic_vector(LOG2_CEIL(LW_MAX-1)-1 downto 0);
        addr_wr   : in  std_logic_vector(LOG2_CEIL(LW_MAX-1)-1 downto 0);
        din       : in  std_logic_vector(DWF-1 downto 0);
        dout      : out std_logic_vector(DWF-1 downto 0)
);
end lbuff_mem;

architecture rtl of lbuff_mem is
attribute syn_hier : string;
attribute syn_hier of rtl: architecture is "hard";

constant CONST_0  : std_logic_vector(127 downto 0) := x"00000000000000000000000000000000";

type array_LBUFF_S is array (LW_MAX-1 downto 0) of STD_LOGIC_VECTOR(DWF-1 downto 0);
constant  LBUFF_init    : std_logic_vector(DWF-1 downto 0) := (others => '0');
signal memory : array_LBUFF_S := (others =>LBUFF_init);
attribute syn_ramstyle : string;
attribute syn_ramstyle of memory : signal is "no_rw_check" ;

signal mem_dout : STD_LOGIC_VECTOR(DWF-1 downto 0);
attribute syn_pipeline : boolean;
attribute syn_pipeline of mem_dout : signal is false;

signal mem_dout_v4 : STD_LOGIC_VECTOR(DWF-1 downto 0);   

begin

-- write
process(clk)
begin
if (clk'event and clk='1') then
   if (wr_en='1') then
      memory(CONV_INTEGER(addr_wr)) <= din;
   end if;
end if;
end process;

process(clk)
begin
if (clk'event and clk='1') then
   if (en='1') then
      mem_dout <= memory(CONV_INTEGER(addr_rd));
   end if;
end if;
end process;

process(clk)
begin
if (clk'event and clk='1') then
   if (en='1') then
      mem_dout_v4 <= mem_dout;
   end if;
end if;
end process;

GEN_OUT_V4V5:
if (FAMILY="virtex4" or FAMILY="virtex5") generate
   dout <= mem_dout_v4;
end generate;
GEN_OUT_OTHERS:
if (FAMILY/="virtex4" and FAMILY/="virtex5") generate
   dout <= mem_dout;
end generate;

end rtl;