test.v

来自「用Verilog实现的移位寄存器」· Verilog 代码 · 共 60 行

`timescale 1ns/1ns
module test();

  // Signal declaration
    reg[7:0] data_in;
    reg din,rst,load,opcode,start;
    wire[7:0] data_out;

  // Instance
	shift_register uut(data_out,data_in,din,rst,load,opcode,clk);
	
  nand #10 (clk, clk, start);  //a 20ns clock oscillator

  initial               //initialize the clock oscillator
    begin
      start = 0;
      #10 start = 1;
    end

  // Apply Stimulus
  initial
    begin
      rst = 0;
      load = 0;
      data_in = 8'h53; 
      din=1;
      opcode=0;         
      #15 rst = 1;
      
      @(negedge clk)
        load=1; 
             
      @(negedge clk)
        load=0;
        
      @(negedge clk)
        opcode=1; 
                
      @(negedge clk)
        load=1;
        data_in = 8'ha5;
        din=0; 
             
      @(negedge clk)
        load=0;   
      
      @(negedge clk)
        opcode=0;
          
     #30 $finish;              // finish simulation
    end
  
  //Create a simulation database
  initial
  begin
    $shm_open("file.shm");  //Open a waveform database
    $shm_probe("A");  //Probe all nodes in this module
  end      
 
endmodule