test3232hv.vhd

VHDL实例

--与AVR通讯协议
--*************************************************************************
--------------------------------------------------
--|ON/OFF(1bit)|out channal(5bit)|in channal(5bit)|
--------------------------------------------------
--ON/OFF 1 -> OFF   0 -> ON
--in/out channal first bit is high bit
--数据上升沿有效，注意！数据进入FPGA前还经过7404，要反向！！！！！
--***************************************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_arith.all;

entity testhv3232 is

   PORT(CLK,SDATA,LATCH : IN STD_LOGIC;
 	    tp     : out std_logic;                       -- for test
		data_in : out std_logic_vector(10 downto 0);  -- for test
 		HV_IN  : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
	    HV_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
	   );
end testhv3232;

architecture v1 of testhv3232 is

type   regs_type	is array (0 to 31) of integer range 0 to 31;
signal status			: regs_type;      --state reg
signal flag             : std_logic_vector(31 downto 0);

begin
tp <= hv_in(16);

 P_DATA_BUFF : PROCESS(CLK,LATCH)
 VARIABLE DATA_TEMP : STD_LOGIC_VECTOR(10 DOWNTO 0);
 BEGIN
  IF LATCH = '1' THEN
     data_in <= data_temp;
     status(conv_integer(data_temp(9 downto 5))) <= conv_integer(data_temp(4 downto 0));
     flag(conv_integer(data_temp(9 downto 5))) <= data_temp(10);
  ELSIF CLK'EVENT AND CLK = '0' THEN
      	DATA_TEMP(10 DOWNTO 1) := DATA_TEMP(9 DOWNTO 0);
      	DATA_TEMP(0) := not SDATA;
  END IF;
 END PROCESS P_DATA_BUFF;

 switch_module:
	process(status,flag,HV_IN)
		variable index	: integer range 0 to 31;
	begin
		for i in 0 to 31 loop
			if flag(i) = '0'	then
				index := status(i);
				HV_OUT(i) <= NOT HV_IN(index);
			else
				HV_OUT(i) <= '0';
			end if;
		end loop;		
	end process switch_module;

end v1;