test3232hv.v

VHDL实例

// File translated by VhdlToVerilog v0.1
// Vhdl to Verilog RTL transformer
// Release: Brier EDA Studio 
// *** All Rights Reserved By Brier Van ***
/*
LIBRARY IEEE;
*/
/*
USE IEEE.STD_LOGIC_1164.ALL;
*/
/*
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
*/
/*
use ieee.std_logic_arith.all;
*/
//与AVR通讯协议
//*************************************************************************
//------------------------------------------------
//|ON/OFF(1bit)|out channal(5bit)|in channal(5bit)|
//------------------------------------------------
//ON/OFF 1 -> OFF   0 -> ON
//in/out channal first bit is high bit
//数据上升沿有效，注意！数据进入FPGA前还经过7404，要反向！！！！！
//***************************************************************************

module testhv3232(
CLK,
SDATA,
LATCH,
tp,
data_in,
HV_IN,
HV_OUT
);

input CLK, SDATA, LATCH;
output tp;
// for test
output[10:0]data_in;
// for test
input[31:0]HV_IN;
output[31:0]HV_OUT;


wire   CLK;
wire   SDATA;
wire   LATCH;
wire   tp;
reg  [10:0]data_in;
wire  [31:0]HV_IN;
reg  [31:0]HV_OUT;


reg [0:31]status[0:31];
//state reg
reg [31:0]flag;
integer i;

  assign tp = hv_in[16];
  always @(posedge LATCH or negedge CLK)
  begin
    reg [10:0]DATA_TEMP;

    if(LATCH == 1'b 1)
    begin
      data_in <= data_temp;
      status[conv_integer[data_temp[9:5]]] <= conv_integer[data_temp[4:0]];
      flag[conv_integer[data_temp[9:5]]] <= data_temp[10];
    end
    else 
    begin
      DATA_TEMP[10:1] = DATA_TEMP[9:0];
      DATA_TEMP[0] =  ~SDATA;
    end
  end

  always @(status or flag or HV_IN)
  begin
    reg [0:31]index;

    for(i=0;i<=31;i=i+1)
    begin
      if(flag[i] == 1'b 0)
      begin
        index = status[i];
        HV_OUT[i] <=  ~HV_IN[index];
      end
      else
      begin
        HV_OUT[i] <= 1'b 0;
      end
    end
  end


endmodule