📄 regkeys
字号:
prop_439_val"Yes"sprop_43_namePROP_XPORTlistInpFilessprop_43_val"false"sprop_440_namePROP_XplorerNumIterationssprop_440_val"7"sprop_441_namePROP_XplorerEnableRetimingsprop_441_val"true"sprop_442_namePROP_XplorerWarnToBackupsprop_442_val"true"sprop_443_namePROP_XplorerOtherCmdLineOptionssprop_443_val""sprop_444_namePROP_PrecNumOfSumPathssprop_444_val"10"sprop_445_namePROP_PrecNumOfCriticalPathssprop_445_val"1"sprop_446_namePROP_xilxMapPackfactorsprop_446_val"100"sprop_447_namePROP_MapRetimingsprop_447_val"false"sprop_448_namePROP_MapEquivalentRegisterRemovalsprop_448_val"true"sprop_449_namePROP_parTimingModesprop_449_val"Performance Evaluation"sprop_44_namePROP_SimModelGenerateTestbenchFilesprop_44_val"false"sprop_450_namePROP_mpprViewParRptForSelRsltsprop_450_val""sprop_451_namePROP_mpprViewPadRptForSelRsltsprop_451_val""sprop_452_namePROP_xilxBitgCfg_GenOpt_DbgBitStrsprop_452_val"false"sprop_453_namePROP_xilxBitgReadBk_GenBitStrsprop_453_val"false"sprop_454_namePROP_xilxBitgCfg_GenOpt_LogicAllocFilesprop_454_val"false"sprop_455_namePROP_xilxBitgCfg_GenOpt_MaskFilesprop_455_val"false"sprop_456_namePROP_AceActiveNamesprop_456_val""sprop_457_namePROP_impactConfigFileNamesprop_457_val""sprop_458_namePROP_SynthRAMStylesprop_458_val"Auto"sprop_459_namePROP_xstROMStylesprop_459_val"Auto"sprop_45_namePROP_SimModelInsertBuffersPulseSwallowsprop_45_val"false"sprop_460_namePROP_SynthMuxStylesprop_460_val"Auto"sprop_461_namePROP_xstMoveFirstFfStagesprop_461_val"true"sprop_462_namePROP_xstMoveLastFfStagesprop_462_val"true"sprop_463_namePROP_MapPowerReductionsprop_463_val"false"sprop_464_namePROP_MapPowerActivityFile_virtex5sprop_464_val""sprop_465_namePROP_MapExtraEffort_virtex5sprop_465_val"None"sprop_466_namePROPEXT_mapTimingMode_virtex5sprop_466_val"Performance Evaluation"sprop_467_namePROPEXT_xilxPAReffortLevel_virtex5sprop_467_val"Standard"sprop_468_namePROPEXT_parGenAsyDlyRpt_virtex5sprop_468_val"false"sprop_469_namePROPEXT_parGenClkRegionRpt_virtex5sprop_469_val"false"sprop_46_namePROP_SimModelOtherNetgenOptssprop_46_val""sprop_470_namePROPEXT_parGenTimingRpt_virtex5sprop_470_val"true"sprop_471_namePROPEXT_parGenSimModel_virtex5sprop_471_val"false"sprop_472_namePROPEXT_parPowerReduction_virtex5sprop_472_val"false"sprop_473_namePROPEXT_parMpprParIterations_virtex5sprop_473_val"3"sprop_474_namePROPEXT_parMpprResultsToSave_virtex5sprop_474_val""sprop_475_namePROPEXT_parMpprResultsDirectory_virtex5sprop_475_val""sprop_476_namePROPEXT_parMpprNodelistFile_virtex5sprop_476_val""sprop_477_namePROP_xilxBitgCfg_GenOpt_DbgBitStr_virtex5sprop_477_val"false"sprop_478_namePROP_xilxBitgCfg_BPI_First_Read_Cycle_virtex5sprop_478_val"2"sprop_479_namePROP_xilxBitgReadBk_GenBitStr_virtex5sprop_479_val"false"sprop_47_namePROP_SimModelRetainHierarchysprop_47_val"true"sprop_480_namePROP_xilxBitgCfg_GenOpt_LogicAllocFile_virtex5sprop_480_val"false"sprop_481_namePROP_xilxBitgCfg_GenOpt_MaskFile_virtex5sprop_481_val"false"sprop_482_namePROP_bitgen_Encrypt_Encrypt_virtex5sprop_482_val"false"sprop_483_namePROP_xilxMapPackfactor_virtex5sprop_483_val"0"sprop_484_namePROPEXT_SynthFrequencySyn_virtex5sprop_484_val"0.0"sprop_485_namePROP_FitterOptimization_xpla3sprop_485_val"Density"sprop_486_namePROP_xcpldFitDesPtermLmt_xbrsprop_486_val"28"sprop_487_namePROP_xcpldFitDesInReg_xbrsprop_487_val"true"sprop_488_namePROP_MapSmartGuideFileNamesprop_488_val"DDR_TX_TEST_guide.ncd"sprop_489_namePROP_ParSmartGuideFileNamesprop_489_val"DDR_TX_TEST_guide.ncd"sprop_48_namePROP_CorgenRegenCoresprop_48_val"Under Current Project Setting"sprop_490_namePROP_DevFamilyPMNamesprop_490_val"virtex5"sprop_491_namePROP_DevDevicesprop_491_val"xc5vfx130t"sprop_492_namePROP_CompxlibSimPathsprop_492_val"d:/Modeltech_6.1f/win32"sprop_493_namePROP_CompxlibLangsprop_493_val"All"sprop_494_namePROP_SimModelGenMultiHierFilesprop_494_val"false"sprop_495_namePROP_ISimSimulationRunTime_par_tbsprop_495_val"1000 ns"sprop_496_namePROP_ISimSimulationRunTime_par_tbwsprop_496_val"1000 ns"sprop_497_namePROP_ISimSimulationRunTime_behav_tbsprop_497_val"1000 ns"sprop_498_namePROP_ISimSimulationRunTime_behav_tbwsprop_498_val"1000 ns"sprop_499_namePROP_ISimVCDFileName_par_tbsprop_499_val"xpower.vcd"sprop_49_namePROP_SynthOptsprop_49_val"Speed"sprop_4_namePROP_HierarchicalProjectTypesprop_4_val"N/A"sprop_500_namePROP_ISimVCDFileName_par_tbwsprop_500_val"xpower.vcd"sprop_501_namePROP_CompxlibSmartModelssprop_501_val"true"sprop_502_namePROP_CompxlibUpdateIniForSmartModelsprop_502_val"false"sprop_503_namePROP_MapPowerActivityFilesprop_503_val""sprop_504_namePROPEXT_xilxPARextraEffortLevel_virtex5sprop_504_val"None"sprop_505_namePROPEXT_parPowerActivityFile_virtex5sprop_505_val""sprop_506_namePROP_xilxBitgCfg_Fallback_Reconfig_virtex5sprop_506_val"Enable"sprop_507_namePROP_bitgen_Encrypt_key0_virtex5sprop_507_val""sprop_508_namePROP_bitgen_Encrypt_keyFile_virtex5sprop_508_val""sprop_509_namePROP_DevPackagesprop_509_val"ff1738"sprop_50_namePROP_SynthOptEffortsprop_50_val"Normal"sprop_510_namePROP_Synthesis_Toolsprop_510_val"XST (VHDL/Verilog)"sprop_511_namePROP_CompxlibUniSimLibsprop_511_val"true"sprop_512_namePROP_CompxlibUni9000Libsprop_512_val"true"sprop_513_namePROP_DevSpeedsprop_513_val"-1"sprop_514_namePROP_PreferredLanguagesprop_514_val"Verilog"sprop_515_namePROP_HdlTemplateLangsprop_515_val"Verilog"sprop_516_namePROP_schFuncModelTargetLangsprop_516_val"Verilog"sprop_517_namePROP_schInstTempTargetLangsprop_517_val"Verilog"sprop_518_namePROP_hdlInstTempTargetLangsprop_518_val"Verilog"sprop_519_namePROP_ChangeDevSpeedsprop_519_val"-1"sprop_51_namePROP_xstUseSynthConstFilesprop_51_val"true"sprop_520_namePROP_SimModelTargetsprop_520_val"Verilog"sprop_521_namePROP_xawHdlSourceTargetLangsprop_521_val"Verilog"sprop_522_namePROP_tbwTestbenchTargetLangsprop_522_val"Verilog"sprop_523_namePROP_coregenFuncModelTargetLangsprop_523_val"Verilog"sprop_524_namePROP_xmpInstTempTargetLangsprop_524_val"Verilog"sprop_525_namePROP_sysgenInstTempTargetLangsprop_525_val"Verilog"sprop_526_namePROP_xilxPreTrceSpeedsprop_526_val"-1"sprop_527_namePROP_xilxPostTrceSpeedsprop_527_val"-1"sprop_528_namePROP_HdlTemplateNamesprop_528_val"DDR_TX_TEST.v"sprop_529_namePROP_SimModelRenTopLevArchTosprop_529_val"Structure"sprop_52_namePROP_xstLibSearchOrdersprop_52_val""sprop_530_namePROP_SimModelGenArchOnlysprop_530_val"false"sprop_531_namePROP_SimModelOutputExtIdentsprop_531_val"false"sprop_532_namePROP_SimModelRenTopLevModsprop_532_val""sprop_533_namePROP_SimModelIncUselibDirInVerilogFilesprop_533_val"false"sprop_534_namePROP_SimModelIncSdfAnnInVerilogFilesprop_534_val"true"sprop_535_namePROP_SimModelNoEscapeSignalsprop_535_val"false"sprop_536_namePROP_netgenPostXlateSimModelNamesprop_536_val"DDR_TX_TEST_translate.v"sprop_537_namePROP_netgenPostMapSimModelNamesprop_537_val"DDR_TX_TEST_map.v"sprop_538_namePROP_netgenPostParSimModelNamesprop_538_val"DDR_TX_TEST_timesim.v"sprop_539_namePROP_bencherPostXlateTestbenchNamesprop_539_val"TB_TX_RX.translate_tfw"sprop_53_namePROP_xstCasesprop_53_val"Maintain"sprop_540_namePROP_bencherPostMapTestbenchNamesprop_540_val"TB_TX_RX.map_tfw"sprop_541_namePROP_bencherPostParTestbenchNamesprop_541_val"TB_TX_RX.timesim_tfw"sprop_542_namePROP_SimModelIncSimprimInVerilogFilesprop_542_val"false"sprop_543_namePROP_SimModelIncUnisimInVerilogFilesprop_543_val"false"sprop_544_namePROP_netgenPostSynthesisSimModelNamesprop_544_val"DDR_TX_TEST_synthesis.v"sprop_545_namePROP_SimModelAutoInsertGlblModuleInNetlistsprop_545_val"true"sprop_546_namePROP_PostXlateSimModelNamesprop_546_val"DDR_TX_TEST_translate.v"sprop_547_namePROP_PostMapSimModelNamesprop_547_val"DDR_TX_TEST_map.v"sprop_548_namePROP_PostParSimModelNamesprop_548_val"DDR_TX_TEST_timesim.v"sprop_549_namePROP_PostParSimModelNamesprop_549_val"DDR_TX_TEST_timesim.v"sprop_54_namePROP_xstWorkDirsprop_54_val"./xst"sprop_550_namePROP_PostParSimModelNamesprop_550_val"DDR_TX_TEST_timesim.v"sprop_551_namePROP_tbwPostXlateTestbenchNamesprop_551_val"TB_TX_RX.translate_tfw"sprop_552_namePROP_tbwPostXlateTestbenchNamesprop_552_val"TB_TX_RX.translate_tfw"sprop_553_namePROP_tbwPostMapTestbenchNamesprop_553_val"TB_TX_RX.map_tfw"sprop_554_namePROP_tbwPostMapTestbenchNamesprop_554_val"TB_TX_RX.map_tfw"sprop_555_namePROP_tbwPostParTestbenchNamesprop_555_val"TB_TX_RX.timesim_tfw"sprop_556_namePROP_tbwPostParTestbenchNamesprop_556_val"TB_TX_RX.timesim_tfw"sprop_557_namePROP_tbwPostParTestbenchNamesprop_557_val"TB_TX_RX.timesim_tfw"sprop_558_namePROP_tbwPostParTestbenchNamesprop_558_val"TB_TX_RX.timesim_tfw"sprop_559_namePROP_PostSynthesisSimModelNamesprop_559_val"DDR_TX_TEST_synthesis.v"sprop_55_namePROP_xstIniFilesprop_55_val""sprop_560_namePROP_SimModelBringOutGtsNetAsAPortsprop_560_val"false"sprop_561_namePROP_SimModelBringOutGsrNetAsAPortsprop_561_val"false"sprop_562_namePROP_netgenRenameTopLevEntTosprop_562_val""sprop_563_namePROP_SimModelPathUsedInSdfAnnsprop_563_val"Default"sprop_56_namePROP_xstVerilog2001sprop_56_val"true"sprop_57_namePROP_xstVeriIncludeDir_Globalsprop_57_val""sprop_58_namePROP_xstUserCompileListsprop_58_val""sprop_59_namePROP_xstGenericsParameterssprop_59_val""sprop_5_namePROP_ProjectGeneratorTypesprop_5_val"ProjNav"sprop_60_namePROP_xstVerilogMacrossprop_60_val""sprop_61_namePROP_xst_otherCmdLineOptionssprop_61_val""sprop_62_namePROP_xstGenerateRTLNetlistsprop_62_val"Yes"sprop_63_namePROP_xstHierarchySeparatorsprop_63_val"/"sprop_64_namePROP_xstBusDelimitersprop_64_val"<>"sprop_65_namePROP_SynthFsmEncodesprop_65_val"Auto"sprop_66_namePROP_SynthCaseImplStylesprop_66_val"None"sprop_67_namePROP_SynthResSharingsprop_67_val"true"sprop_68_namePROP_SynthExtractMuxsprop_68_val"Yes"sprop_69_namePROP_xilxSynthAddIObufsprop_69_val"true"sprop_6_namePROP_Parse_Targetsprop_6_val"synthesis"sprop_70_namePROP_xstEquivRegRemovalsprop_70_val"true"sprop_71_namePROP_SynthMultStylesprop_71_val"LUT"sprop_72_namePROP_ISimUutInstNamesprop_72_val"UUT"sprop_73_namePROP_ISimUseCustomSimCmdFile_par_tbsprop_73_val"false"sprop_74_namePROP_ISimUseCustomSimCmdFile_par_tbwsprop_74_val"false"sprop_75_namePROP_ISimUseCustomSimCmdFile_behav_tbsprop_75_val"false"sprop_76_namePROP_ISimUseCustomSimCmdFile_behav_tbwsprop_76_val"false"sprop_77_namePROP_ISimUseCustomSimCmdFile_gen_tbwsprop_77_val"false"sprop_78_namePROP_ISimUseCustomSimCmdFile_launchsprop_78_val"false"sprop_79_namePROP_isimIncreCompilationsprop_79_val"true"sprop_7_namePROP_Top_Level_Module_Typesprop_7_val"HDL"sprop_80_namePROP_isimCompileForHdlDebugsprop_80_val"true"sprop_81_namePROP_ISimSDFTimingToBeReadsprop_81_val"Setup Time"sprop_82_namePROP_isimValueRangeChecksprop_82_val"false"sprop_83_namePROP_isimSpecifySearchDirectorysprop_83_val""sprop_84_namePROP_ISimSpecifySearchDirectoryChkSyntaxsprop_84_val""sprop_85_namePROP_isimSpecifyDefMacroAndValuesprop_85_val""sprop_86_namePROP_ISimSpecifyDefMacroAndValueChkSyntaxsprop_86_val""sprop_87_namePROP_ISimLibSearchOrderFilesprop_87_val""sprop_88_namePROP_ISimUseCustomCompilationOrdersprop_88_val"false"sprop_89_namePROP_ISimOtherCompilerOptions_behavsprop_89_val""sprop_8_namePROP_SynthTopsprop_8_val"Module|DDR_TX_TEST"sprop_90_namePROP_ISimOtherCompilerOptions_parsprop_90_val""sprop_91_namePROP_ISimOtherCompilerOptions_fitsprop_91_val""sprop_92_namePROP_DefaultTBNamesprop_92_val"Default"sprop_93_namePROP_ibiswriterShowAllModelssprop_93_val"false"sprop_94_namePROP_ImpactProjectFilesprop_94_val"Default"sprop_95_namePROP_ngdbuild_otherCmdLineOptionssprop_95_val""sprop_96_namePROP_SynthXORCollapsesprop_96_val"true"sprop_97_namePROP_xilxNgdbld_AULsprop_97_val"false"sprop_98_namePROP_xilxNgdbldMacrosprop_98_val""sprop_99_namePROP_xilxSynthKeepHierarchysprop_99_val"No"sprop_9_namePROP_BehavioralSimTopsprop_9_val"Module|TB_TX_RX"s
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -