video.map.qmsg

显示总线扩展的_VHDL代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 10 12:02:31 2004 " "Info: Processing started: Mon May 10 12:02:31 2004" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off VIDEO -c VIDEO " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off VIDEO -c VIDEO" {  } {  } 0}
{ "Warning" "WSGN_NO_ELA_SUPPORT" " " "Warning: SignalTap II Logic Analyzer is not supported for selected device family-- SignalTap II or debug node instance  is disabled" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "VIDEO.vhd 2 1 " "Info: Using design file VIDEO.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 VIDEO-Control " "Info: Found design unit 1: VIDEO-Control" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "VIDEO-Control" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 20 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 VIDEO " "Info: Found entity 1: VIDEO" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "VIDEO" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "95 " "Info: Implemented 95 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "42 " "Info: Implemented 42 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "42 " "Info: Implemented 42 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon May 10 12:02:35 2004 " "Info: Processing ended: Mon May 10 12:02:35 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}