video.tan.qmsg

显示总线扩展的_VHDL代码

{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node CLK is an undefined clock" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 15 -1 0 } } { "d:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "d:/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register DISPLAYF\[0\]~reg0 register DISPLAYF\[0\]~reg0 76.92 MHz 13.0 ns Internal " "Info: Clock CLK has Internal fmax of 76.92 MHz between source register DISPLAYF\[0\]~reg0 and destination register DISPLAYF\[0\]~reg0 (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DISPLAYF\[0\]~reg0 1 REG LC35 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC35; Fanout = 4; REG Node = 'DISPLAYF\[0\]~reg0'" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "" { DISPLAYF[0]~reg0 } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.000 ns DISPLAYF\[0\]~reg0 2 REG LC35 4 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.000 ns; Loc. = LC35; Fanout = 4; REG Node = 'DISPLAYF\[0\]~reg0'" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "8.000 ns" { DISPLAYF[0]~reg0 DISPLAYF[0]~reg0 } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 100.00 % " "Info: Total cell delay = 8.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "8.000 ns" { DISPLAYF[0]~reg0 DISPLAYF[0]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 10.000 ns + Shortest register " "Info: + Shortest clock path from clock CLK to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK Pin_48 42 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_48; Fanout = 42; CLK Node = 'CLK'" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns DISPLAYF\[0\]~reg0 2 REG LC35 4 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC35; Fanout = 4; REG Node = 'DISPLAYF\[0\]~reg0'" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "8.000 ns" { CLK DISPLAYF[0]~reg0 } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "10.000 ns" { CLK DISPLAYF[0]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 10.000 ns - Longest register " "Info: - Longest clock path from clock CLK to source register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK Pin_48 42 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_48; Fanout = 42; CLK Node = 'CLK'" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns DISPLAYF\[0\]~reg0 2 REG LC35 4 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC35; Fanout = 4; REG Node = 'DISPLAYF\[0\]~reg0'" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "8.000 ns" { CLK DISPLAYF[0]~reg0 } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "10.000 ns" { CLK DISPLAYF[0]~reg0 } "NODE_NAME" } } }  } 0}  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "10.000 ns" { CLK DISPLAYF[0]~reg0 } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "10.000 ns" { CLK DISPLAYF[0]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 26 -1 0 } }  } 0}  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "8.000 ns" { DISPLAYF[0]~reg0 DISPLAYF[0]~reg0 } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "10.000 ns" { CLK DISPLAYF[0]~reg0 } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "10.000 ns" { CLK DISPLAYF[0]~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "DISPLAYA\[0\]~reg0 DATAIN\[0\] CLK 4.000 ns register " "Info: tsu for register DISPLAYA\[0\]~reg0 (data pin = DATAIN\[0\], clock pin = CLK) is 4.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns DATAIN\[0\] 1 PIN Pin_33 12 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_33; Fanout = 12; PIN Node = 'DATAIN\[0\]'" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "" { DATAIN[0] } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns DISPLAYA\[0\]~reg0 2 REG LC94 4 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC94; Fanout = 4; REG Node = 'DISPLAYA\[0\]~reg0'" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "8.000 ns" { DATAIN[0] DISPLAYA[0]~reg0 } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "10.000 ns" { DATAIN[0] DISPLAYA[0]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 10.000 ns - Shortest register " "Info: - Shortest clock path from clock CLK to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK Pin_48 42 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_48; Fanout = 42; CLK Node = 'CLK'" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns DISPLAYA\[0\]~reg0 2 REG LC94 4 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC94; Fanout = 4; REG Node = 'DISPLAYA\[0\]~reg0'" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "8.000 ns" { CLK DISPLAYA[0]~reg0 } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "10.000 ns" { CLK DISPLAYA[0]~reg0 } "NODE_NAME" } } }  } 0}  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "10.000 ns" { DATAIN[0] DISPLAYA[0]~reg0 } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "10.000 ns" { CLK DISPLAYA[0]~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK DISPLAYF\[0\] DISPLAYF\[0\]~reg0 15.000 ns register " "Info: tco from clock CLK to destination pin DISPLAYF\[0\] through register DISPLAYF\[0\]~reg0 is 15.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 10.000 ns + Longest register " "Info: + Longest clock path from clock CLK to source register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK Pin_48 42 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_48; Fanout = 42; CLK Node = 'CLK'" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns DISPLAYF\[0\]~reg0 2 REG LC35 4 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC35; Fanout = 4; REG Node = 'DISPLAYF\[0\]~reg0'" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "8.000 ns" { CLK DISPLAYF[0]~reg0 } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "10.000 ns" { CLK DISPLAYF[0]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest register pin " "Info: + Longest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DISPLAYF\[0\]~reg0 1 REG LC35 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC35; Fanout = 4; REG Node = 'DISPLAYF\[0\]~reg0'" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "" { DISPLAYF[0]~reg0 } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns DISPLAYF\[0\] 2 PIN Pin_31 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = Pin_31; Fanout = 0; PIN Node = 'DISPLAYF\[0\]'" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "4.000 ns" { DISPLAYF[0]~reg0 DISPLAYF[0] } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "4.000 ns" { DISPLAYF[0]~reg0 DISPLAYF[0] } "NODE_NAME" } } }  } 0}  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "10.000 ns" { CLK DISPLAYF[0]~reg0 } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "4.000 ns" { DISPLAYF[0]~reg0 DISPLAYF[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "DISPLAYA\[0\]~reg0 DATAIN\[0\] CLK 4.000 ns register " "Info: th for register DISPLAYA\[0\]~reg0 (data pin = DATAIN\[0\], clock pin = CLK) is 4.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 10.000 ns + Longest register " "Info: + Longest clock path from clock CLK to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK Pin_48 42 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_48; Fanout = 42; CLK Node = 'CLK'" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns DISPLAYA\[0\]~reg0 2 REG LC94 4 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC94; Fanout = 4; REG Node = 'DISPLAYA\[0\]~reg0'" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "8.000 ns" { CLK DISPLAYA[0]~reg0 } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "10.000 ns" { CLK DISPLAYA[0]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns DATAIN\[0\] 1 PIN Pin_33 12 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_33; Fanout = 12; PIN Node = 'DATAIN\[0\]'" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "" { DATAIN[0] } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns DISPLAYA\[0\]~reg0 2 REG LC94 4 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC94; Fanout = 4; REG Node = 'DISPLAYA\[0\]~reg0'" {  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "8.000 ns" { DATAIN[0] DISPLAYA[0]~reg0 } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" "" "" { Text "D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "10.000 ns" { DATAIN[0] DISPLAYA[0]~reg0 } "NODE_NAME" } } }  } 0}  } { { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "10.000 ns" { CLK DISPLAYA[0]~reg0 } "NODE_NAME" } } } { "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" "" "" { Report "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "D:/administrator/My Documents/jianhuade VIDEO APP/db2/db/VIDEO.quartus_db" { Floorplan "" "" "10.000 ns" { DATAIN[0] DISPLAYA[0]~reg0 } "NODE_NAME" } } }  } 0}