📄 video.map.rpt
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Analysis & Synthesis report for VIDEO
Mon May 10 12:02:35 2004
Version 4.0 Build 190 1/28/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Default Parameter Settings
5. Hierarchy
6. Analysis & Synthesis Resource Utilization by Entity
7. Analysis & Synthesis Equations
8. Analysis & Synthesis Files Read
9. Analysis & Synthesis Resource Usage Summary
10. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+---------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+---------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon May 10 12:02:35 2004 ;
; Revision Name ; VIDEO ;
; Top-level Entity Name ; VIDEO ;
; Family ; MAX7000S ;
; Total macrocells ; 42 ;
; Total pins ; 53 ;
+-----------------------------+---------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+------------------------------------------------------------------------------------------------------
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------+--------------+---------------+
; Optimization Technique -- MAX 7000B/7000AE/3000A ; Area ; Speed ;
; Top-level entity name ; VIDEO ; ;
; Family name ; MAX7000S ; Stratix ;
; Disk space/compilation speed tradeoff ; Smart ; Normal ;
; Auto Resource Sharing ; Off ; Off ;
; Remove Duplicate Logic ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto Parallel Expanders ; On ; On ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4 ; 4 ;
; Auto Logic Cell Insertion ; On ; On ;
; Allow XOR Gate Usage ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Off ; Off ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Auto ; Auto ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore CARRY Buffers ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Power-Up Don't Care ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; State Machine Processing ; Auto ; Auto ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; Preserve fewer node names ; On ; On ;
; Create Debugging Nodes for IP Cores ; off ; off ;
+----------------------------------------------------------------------+--------------+---------------+
+-------------------------------------------------+
; Analysis & Synthesis Default Parameter Settings ;
+--------------------------------------------------
; Name ; Setting ;
+--------------------+----------------------------+
; CARRY_CHAIN ; MANUAL ;
; CASCADE_CHAIN ; MANUAL ;
; OPTIMIZE_FOR_SPEED ; 1 ;
; STYLE ; FAST ;
+--------------------+----------------------------+
+------------+
; Hierarchy ;
+------------+
VIDEO
+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-----------------------------------------------------------------------
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |VIDEO ; 42 ; 53 ; |VIDEO ;
+----------------------------+------------+------+---------------------+
+---------------------------------+
; Analysis & Synthesis Equations ;
+---------------------------------+
The equations can be found in D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.map.eqn.
+------------------------------------------------------------------------+
; Analysis & Synthesis Files Read ;
+-------------------------------------------------------------------------
; File Name ; Read ;
+-----------------------------------------------------------------+------+
; D:/administrator/My Documents/jianhuade VIDEO APP/db2/VIDEO.vhd ; Read ;
+-----------------------------------------------------------------+------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------------------------------
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 42 ;
; Total registers ; 42 ;
; I/O pins ; 53 ;
; Maximum fan-out node ; CLK ;
; Maximum fan-out ; 42 ;
; Total fan-out ; 294 ;
; Average fan-out ; 3.09 ;
+----------------------+----------------------+
+--------------------------------+
; Analysis & Synthesis Messages ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
Info: Processing started: Mon May 10 12:02:31 2004
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off VIDEO -c VIDEO
Warning: SignalTap II Logic Analyzer is not supported for selected device family-- SignalTap II or debug node instance is disabled
Info: Using design file VIDEO.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: VIDEO-Control
Info: Found entity 1: VIDEO
Info: Implemented 95 device resources after synthesis - the final resource count might be different
Info: Implemented 11 input pins
Info: Implemented 42 output pins
Info: Implemented 42 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Processing ended: Mon May 10 12:02:35 2004
Info: Elapsed time: 00:00:04
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