📄 video.tan.rpt
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; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYC[3]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYC[2]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYC[1]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYC[0]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYD[6]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYD[5]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYD[4]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYD[3]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYD[2]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYD[1]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYD[0]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYE[6]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYE[5]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYE[4]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYE[3]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYE[2]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYE[1]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYE[0]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYF[6]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYF[5]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYF[4]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYF[3]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYF[2]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYF[1]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; ADDRESS[0] ; DISPLAYF[0]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; DATAIN[6] ; DISPLAYA[6]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; DATAIN[6] ; DISPLAYB[6]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; DATAIN[6] ; DISPLAYC[6]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; DATAIN[6] ; DISPLAYD[6]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; DATAIN[6] ; DISPLAYE[6]~reg0 ; CLK ;
; N/A ; None ; 4.000 ns ; DATAIN[6] ; DISPLAYF[6]~reg0 ; CLK ;
+---------------+-------------+-----------+------------+------------------+----------+
+-------------------------------------------------------------------------------------------------+
; Minimum tco ;
+--------------------------------------------------------------------------------------------------
; Minimum Slack ; Required Min tco ; Actual Min tco ; From ; To ; From Clock ;
+---------------+------------------+----------------+------------------+-------------+------------+
; N/A ; None ; 15.000 ns ; DISPLAYA[6]~reg0 ; DISPLAYA[6] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYA[5]~reg0 ; DISPLAYA[5] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYA[4]~reg0 ; DISPLAYA[4] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYA[3]~reg0 ; DISPLAYA[3] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYA[2]~reg0 ; DISPLAYA[2] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYA[1]~reg0 ; DISPLAYA[1] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYA[0]~reg0 ; DISPLAYA[0] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYB[6]~reg0 ; DISPLAYB[6] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYB[5]~reg0 ; DISPLAYB[5] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYB[4]~reg0 ; DISPLAYB[4] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYB[3]~reg0 ; DISPLAYB[3] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYB[2]~reg0 ; DISPLAYB[2] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYB[1]~reg0 ; DISPLAYB[1] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYB[0]~reg0 ; DISPLAYB[0] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYC[6]~reg0 ; DISPLAYC[6] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYC[5]~reg0 ; DISPLAYC[5] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYC[4]~reg0 ; DISPLAYC[4] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYC[3]~reg0 ; DISPLAYC[3] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYC[2]~reg0 ; DISPLAYC[2] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYC[1]~reg0 ; DISPLAYC[1] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYC[0]~reg0 ; DISPLAYC[0] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYD[6]~reg0 ; DISPLAYD[6] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYD[5]~reg0 ; DISPLAYD[5] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYD[4]~reg0 ; DISPLAYD[4] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYD[3]~reg0 ; DISPLAYD[3] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYD[2]~reg0 ; DISPLAYD[2] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYD[1]~reg0 ; DISPLAYD[1] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYD[0]~reg0 ; DISPLAYD[0] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYE[6]~reg0 ; DISPLAYE[6] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYE[5]~reg0 ; DISPLAYE[5] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYE[4]~reg0 ; DISPLAYE[4] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYE[3]~reg0 ; DISPLAYE[3] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYE[2]~reg0 ; DISPLAYE[2] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYE[1]~reg0 ; DISPLAYE[1] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYE[0]~reg0 ; DISPLAYE[0] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYF[6]~reg0 ; DISPLAYF[6] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYF[5]~reg0 ; DISPLAYF[5] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYF[4]~reg0 ; DISPLAYF[4] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYF[3]~reg0 ; DISPLAYF[3] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYF[2]~reg0 ; DISPLAYF[2] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYF[1]~reg0 ; DISPLAYF[1] ; CLK ;
; N/A ; None ; 15.000 ns ; DISPLAYF[0]~reg0 ; DISPLAYF[0] ; CLK ;
+---------------+------------------+----------------+------------------+-------------+------------+
+---------------------------+
; Timing Analyzer Messages ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
Info: Processing started: Mon May 10 12:02:41 2004
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off VIDEO -c VIDEO
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node CLK is an undefined clock
Info: Clock CLK has Internal fmax of 76.92 MHz between source register DISPLAYF[0]~reg0 and destination register DISPLAYF[0]~reg0 (period= 13.0 ns)
Info: + Longest register to register delay is 8.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC35; Fanout = 4; REG Node = 'DISPLAYF[0]~reg0'
Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.000 ns; Loc. = LC35; Fanout = 4; REG Node = 'DISPLAYF[0]~reg0'
Info: Total cell delay = 8.000 ns ( 100.00 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock CLK to destination register is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_48; Fanout = 42; CLK Node = 'CLK'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC35; Fanout = 4; REG Node = 'DISPLAYF[0]~reg0'
Info: Total cell delay = 8.000 ns ( 80.00 % )
Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: - Longest clock path from clock CLK to source register is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_48; Fanout = 42; CLK Node = 'CLK'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC35; Fanout = 4; REG Node = 'DISPLAYF[0]~reg0'
Info: Total cell delay = 8.000 ns ( 80.00 % )
Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Micro setup delay of destination is 4.000 ns
Info: tsu for register DISPLAYA[0]~reg0 (data pin = DATAIN[0], clock pin = CLK) is 4.000 ns
Info: + Longest pin to register delay is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_33; Fanout = 12; PIN Node = 'DATAIN[0]'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC94; Fanout = 4; REG Node = 'DISPLAYA[0]~reg0'
Info: Total cell delay = 8.000 ns ( 80.00 % )
Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: + Micro setup delay of destination is 4.000 ns
Info: - Shortest clock path from clock CLK to destination register is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_48; Fanout = 42; CLK Node = 'CLK'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC94; Fanout = 4; REG Node = 'DISPLAYA[0]~reg0'
Info: Total cell delay = 8.000 ns ( 80.00 % )
Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: tco from clock CLK to destination pin DISPLAYF[0] through register DISPLAYF[0]~reg0 is 15.000 ns
Info: + Longest clock path from clock CLK to source register is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_48; Fanout = 42; CLK Node = 'CLK'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC35; Fanout = 4; REG Node = 'DISPLAYF[0]~reg0'
Info: Total cell delay = 8.000 ns ( 80.00 % )
Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Longest register to pin delay is 4.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC35; Fanout = 4; REG Node = 'DISPLAYF[0]~reg0'
Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = Pin_31; Fanout = 0; PIN Node = 'DISPLAYF[0]'
Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: th for register DISPLAYA[0]~reg0 (data pin = DATAIN[0], clock pin = CLK) is 4.000 ns
Info: + Longest clock path from clock CLK to destination register is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_48; Fanout = 42; CLK Node = 'CLK'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC94; Fanout = 4; REG Node = 'DISPLAYA[0]~reg0'
Info: Total cell delay = 8.000 ns ( 80.00 % )
Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: + Micro hold delay of destination is 4.000 ns
Info: - Shortest pin to register delay is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_33; Fanout = 12; PIN Node = 'DATAIN[0]'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC94; Fanout = 4; REG Node = 'DISPLAYA[0]~reg0'
Info: Total cell delay = 8.000 ns ( 80.00 % )
Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: Minimum tco from clock CLK to destination pin DISPLAYA[6] through register DISPLAYA[6]~reg0 is 15.000 ns
Info: + Shortest clock path from clock CLK to source register is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_48; Fanout = 42; CLK Node = 'CLK'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC88; Fanout = 4; REG Node = 'DISPLAYA[6]~reg0'
Info: Total cell delay = 8.000 ns ( 80.00 % )
Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Shortest register to pin delay is 4.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC88; Fanout = 4; REG Node = 'DISPLAYA[6]~reg0'
Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = Pin_57; Fanout = 0; PIN Node = 'DISPLAYA[6]'
Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Mon May 10 12:02:41 2004
Info: Elapsed time: 00:00:00
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