video.tan.qmsg

读屏幕上亮点坐标的VHDL代码

{ "Info" "ITDB_TH_RESULT" "DATAOUT\[9\]~reg0 ADDRESSA\[2\] RCLK 3.000 ns register " "Info: th for register DATAOUT\[9\]~reg0 (data pin = ADDRESSA\[2\], clock pin = RCLK) is 3.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RCLK destination 6.500 ns + Longest register " "Info: + Longest clock path from clock RCLK to destination register is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns RCLK 1 CLK Pin_35 11 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = Pin_35; Fanout = 11; CLK Node = 'RCLK'" {  } { { "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" "" "" { Report "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO.quartus_db" { Floorplan "" "" "" { RCLK } "NODE_NAME" } } } { "E:/jianhuade VIDEO APP/db1/新建文件夹/VIDEO.vhd" "" "" { Text "E:/jianhuade VIDEO APP/db1/新建文件夹/VIDEO.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns DATAOUT\[9\]~reg0 2 REG LC45 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC45; Fanout = 1; REG Node = 'DATAOUT\[9\]~reg0'" {  } { { "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" "" "" { Report "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO.quartus_db" { Floorplan "" "" "6.000 ns" { RCLK DATAOUT[9]~reg0 } "NODE_NAME" } } } { "E:/jianhuade VIDEO APP/db1/新建文件夹/VIDEO.vhd" "" "" { Text "E:/jianhuade VIDEO APP/db1/新建文件夹/VIDEO.vhd" 92 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 84.62 % " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 15.38 % " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0}  } { { "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" "" "" { Report "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO.quartus_db" { Floorplan "" "" "6.500 ns" { RCLK DATAOUT[9]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" {  } { { "E:/jianhuade VIDEO APP/db1/新建文件夹/VIDEO.vhd" "" "" { Text "E:/jianhuade VIDEO APP/db1/新建文件夹/VIDEO.vhd" 92 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns ADDRESSA\[2\] 1 PIN Pin_29 35 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = Pin_29; Fanout = 35; PIN Node = 'ADDRESSA\[2\]'" {  } { { "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" "" "" { Report "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO.quartus_db" { Floorplan "" "" "" { ADDRESSA[2] } "NODE_NAME" } } } { "E:/jianhuade VIDEO APP/db1/新建文件夹/VIDEO.vhd" "" "" { Text "E:/jianhuade VIDEO APP/db1/新建文件夹/VIDEO.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns DATAOUT\[9\]~reg0 2 REG LC45 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC45; Fanout = 1; REG Node = 'DATAOUT\[9\]~reg0'" {  } { { "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" "" "" { Report "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO.quartus_db" { Floorplan "" "" "6.000 ns" { ADDRESSA[2] DATAOUT[9]~reg0 } "NODE_NAME" } } } { "E:/jianhuade VIDEO APP/db1/新建文件夹/VIDEO.vhd" "" "" { Text "E:/jianhuade VIDEO APP/db1/新建文件夹/VIDEO.vhd" 92 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 84.62 % " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 15.38 % " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0}  } { { "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" "" "" { Report "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO.quartus_db" { Floorplan "" "" "6.500 ns" { ADDRESSA[2] DATAOUT[9]~reg0 } "NODE_NAME" } } }  } 0}  } { { "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" "" "" { Report "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO.quartus_db" { Floorplan "" "" "6.500 ns" { RCLK DATAOUT[9]~reg0 } "NODE_NAME" } } } { "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" "" "" { Report "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO.quartus_db" { Floorplan "" "" "6.500 ns" { ADDRESSA[2] DATAOUT[9]~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "RCLK DATAOUT\[9\] DATAOUT\[9\]~reg0 10.000 ns register " "Info: Minimum tco from clock RCLK to destination pin DATAOUT\[9\] through register DATAOUT\[9\]~reg0 is 10.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RCLK source 6.500 ns + Shortest register " "Info: + Shortest clock path from clock RCLK to source register is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns RCLK 1 CLK Pin_35 11 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = Pin_35; Fanout = 11; CLK Node = 'RCLK'" {  } { { "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" "" "" { Report "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO.quartus_db" { Floorplan "" "" "" { RCLK } "NODE_NAME" } } } { "E:/jianhuade VIDEO APP/db1/新建文件夹/VIDEO.vhd" "" "" { Text "E:/jianhuade VIDEO APP/db1/新建文件夹/VIDEO.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns DATAOUT\[9\]~reg0 2 REG LC45 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC45; Fanout = 1; REG Node = 'DATAOUT\[9\]~reg0'" {  } { { "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" "" "" { Report "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO.quartus_db" { Floorplan "" "" "6.000 ns" { RCLK DATAOUT[9]~reg0 } "NODE_NAME" } } } { "E:/jianhuade VIDEO APP/db1/新建文件夹/VIDEO.vhd" "" "" { Text "E:/jianhuade VIDEO APP/db1/新建文件夹/VIDEO.vhd" 92 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 84.62 % " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 15.38 % " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0}  } { { "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" "" "" { Report "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO.quartus_db" { Floorplan "" "" "6.500 ns" { RCLK DATAOUT[9]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "E:/jianhuade VIDEO APP/db1/新建文件夹/VIDEO.vhd" "" "" { Text "E:/jianhuade VIDEO APP/db1/新建文件夹/VIDEO.vhd" 92 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.500 ns + Shortest register pin " "Info: + Shortest register to pin delay is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DATAOUT\[9\]~reg0 1 REG LC45 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC45; Fanout = 1; REG Node = 'DATAOUT\[9\]~reg0'" {  } { { "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" "" "" { Report "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO.quartus_db" { Floorplan "" "" "" { DATAOUT[9]~reg0 } "NODE_NAME" } } } { "E:/jianhuade VIDEO APP/db1/新建文件夹/VIDEO.vhd" "" "" { Text "E:/jianhuade VIDEO APP/db1/新建文件夹/VIDEO.vhd" 92 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns DATAOUT\[9\] 2 PIN Pin_25 0 " "Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = Pin_25; Fanout = 0; PIN Node = 'DATAOUT\[9\]'" {  } { { "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" "" "" { Report "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO.quartus_db" { Floorplan "" "" "1.500 ns" { DATAOUT[9]~reg0 DATAOUT[9] } "NODE_NAME" } } } { "E:/jianhuade VIDEO APP/db1/新建文件夹/VIDEO.vhd" "" "" { Text "E:/jianhuade VIDEO APP/db1/新建文件夹/VIDEO.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" "" "" { Report "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO.quartus_db" { Floorplan "" "" "1.500 ns" { DATAOUT[9]~reg0 DATAOUT[9] } "NODE_NAME" } } }  } 0}  } { { "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" "" "" { Report "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO.quartus_db" { Floorplan "" "" "6.500 ns" { RCLK DATAOUT[9]~reg0 } "NODE_NAME" } } } { "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" "" "" { Report "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "E:/jianhuade VIDEO APP/db1/新建文件夹/db/VIDEO.quartus_db" { Floorplan "" "" "1.500 ns" { DATAOUT[9]~reg0 DATAOUT[9] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 10 19:56:35 2005 " "Info: Processing ended: Fri Jun 10 19:56:35 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}