video.csf.qmsg

在屏幕上形成矩形的VHDL程序

{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 07 18:49:05 2008 " "Info: Processing ended: Fri Mar 07 18:49:05 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 07 18:49:06 2008 " "Info: Processing started: Fri Mar 07 18:49:06 2008" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off VIDEO -c VIDEO " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off VIDEO -c VIDEO" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node CLK is an undefined clock" {  } { { "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/VIDEO.vhd" "" "" { Text "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/VIDEO.vhd" 8 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "VERSYNC " "Info: Assuming node VERSYNC is an undefined clock" {  } { { "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/VIDEO.vhd" "" "" { Text "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/VIDEO.vhd" 11 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "VERSYNC" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register lpm_counter:VER_COUNT_rtl_0\|dffs\[0\] register lpm_counter:VER_COUNT_rtl_0\|dffs\[9\] 76.92 MHz 13.0 ns Internal " "Info: Clock CLK has Internal fmax of 76.92 MHz between source register lpm_counter:VER_COUNT_rtl_0\|dffs\[0\] and destination register lpm_counter:VER_COUNT_rtl_0\|dffs\[9\] (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:VER_COUNT_rtl_0\|dffs\[0\] 1 REG LC1 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 11; REG Node = 'lpm_counter:VER_COUNT_rtl_0\|dffs\[0\]'" {  } { { "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" "" "" { Report "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO.quartus_db" { Floorplan "" "" "" { lpm_counter:VER_COUNT_rtl_0|dffs[0] } "NODE_NAME" } } } { "e:/quartus/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/lpm_counter.tdf" 256 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns lpm_counter:VER_COUNT_rtl_0\|dffs\[9\] 2 REG LC122 2 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC122; Fanout = 2; REG Node = 'lpm_counter:VER_COUNT_rtl_0\|dffs\[9\]'" {  } { { "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" "" "" { Report "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO.quartus_db" { Floorplan "" "" "8.000 ns" { lpm_counter:VER_COUNT_rtl_0|dffs[0] lpm_counter:VER_COUNT_rtl_0|dffs[9] } "NODE_NAME" } } } { "e:/quartus/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/lpm_counter.tdf" 256 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" "" "" { Report "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO.quartus_db" { Floorplan "" "" "8.000 ns" { lpm_counter:VER_COUNT_rtl_0|dffs[0] lpm_counter:VER_COUNT_rtl_0|dffs[9] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 10.000 ns + Shortest register " "Info: + Shortest clock path from clock CLK to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK Pin_36 10 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_36; Fanout = 10; CLK Node = 'CLK'" {  } { { "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" "" "" { Report "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/VIDEO.vhd" "" "" { Text "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/VIDEO.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns lpm_counter:VER_COUNT_rtl_0\|dffs\[9\] 2 REG LC122 2 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC122; Fanout = 2; REG Node = 'lpm_counter:VER_COUNT_rtl_0\|dffs\[9\]'" {  } { { "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" "" "" { Report "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO.quartus_db" { Floorplan "" "" "8.000 ns" { CLK lpm_counter:VER_COUNT_rtl_0|dffs[9] } "NODE_NAME" } } } { "e:/quartus/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/lpm_counter.tdf" 256 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" "" "" { Report "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO.quartus_db" { Floorplan "" "" "10.000 ns" { CLK lpm_counter:VER_COUNT_rtl_0|dffs[9] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 10.000 ns - Longest register " "Info: - Longest clock path from clock CLK to source register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK Pin_36 10 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_36; Fanout = 10; CLK Node = 'CLK'" {  } { { "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" "" "" { Report "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/VIDEO.vhd" "" "" { Text "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/VIDEO.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns lpm_counter:VER_COUNT_rtl_0\|dffs\[0\] 2 REG LC1 11 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC1; Fanout = 11; REG Node = 'lpm_counter:VER_COUNT_rtl_0\|dffs\[0\]'" {  } { { "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" "" "" { Report "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO.quartus_db" { Floorplan "" "" "8.000 ns" { CLK lpm_counter:VER_COUNT_rtl_0|dffs[0] } "NODE_NAME" } } } { "e:/quartus/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/lpm_counter.tdf" 256 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" "" "" { Report "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO.quartus_db" { Floorplan "" "" "10.000 ns" { CLK lpm_counter:VER_COUNT_rtl_0|dffs[0] } "NODE_NAME" } } }  } 0}  } { { "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" "" "" { Report "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO.quartus_db" { Floorplan "" "" "10.000 ns" { CLK lpm_counter:VER_COUNT_rtl_0|dffs[9] } "NODE_NAME" } } } { "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" "" "" { Report "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO.quartus_db" { Floorplan "" "" "10.000 ns" { CLK lpm_counter:VER_COUNT_rtl_0|dffs[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "e:/quartus/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/lpm_counter.tdf" 256 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "e:/quartus/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/lpm_counter.tdf" 256 9 0 } }  } 0}  } { { "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" "" "" { Report "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO.quartus_db" { Floorplan "" "" "8.000 ns" { lpm_counter:VER_COUNT_rtl_0|dffs[0] lpm_counter:VER_COUNT_rtl_0|dffs[9] } "NODE_NAME" } } } { "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" "" "" { Report "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO.quartus_db" { Floorplan "" "" "10.000 ns" { CLK lpm_counter:VER_COUNT_rtl_0|dffs[9] } "NODE_NAME" } } } { "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" "" "" { Report "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO_cmp.qrpt" Compiler "VIDEO" "UNKNOWN" "V1" "e:/weili_an/桌面/研究生视频信号应用实验资料/视频信号应用实验代码/在屏幕上形成矩形的_VHDL代码/db/VIDEO.quartus_db" { Floorplan "" "" "10.000 ns" { CLK lpm_counter:VER_COUNT_rtl_0|dffs[0] } "NODE_NAME" } } }  } 0}