video.vhd

在屏幕上形成矩形的VHDL程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--------------------**********************************************-----------------------
ENTITY VIDEO IS
   PORT(
	    CLK:	IN STD_LOGIC;	--Clock Signal

        COMSYNC:IN STD_LOGIC;	--Composite Sync Signal Input
        VERSYNC:IN STD_LOGIC;	--Vertical  Sync Signal Input
		

		DETECTOUT:OUT STD_LOGIC
--		DATA_IN: IN STD_LOGIC_VECTOR(9 DOWNTO 0);
--		DATABUS: IN STD_LOGIC_VECTOR(2 DOWNTO 0)
        );
END VIDEO;

ARCHITECTURE Control OF VIDEO IS

SIGNAL VER_COUNT:  STD_LOGIC_VECTOR(9 DOWNTO 0);-------行计数器
SIGNAL COM_COUNT:  STD_LOGIC_VECTOR(9 DOWNTO 0);-------场计数器

SIGNAL COM_REG_A: STD_LOGIC_VECTOR(9 DOWNTO 0);------两个场通用寄存器
SIGNAL COM_REG_B: STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL VER_REG_A: STD_LOGIC_VECTOR(9 DOWNTO 0);------两个行通用寄存器
SIGNAL VER_REG_B: STD_LOGIC_VECTOR(9 DOWNTO 0);


BEGIN
--行计数器
	PROCESS(CLK,VERSYNC)                           
	BEGIN

		IF(VERSYNC='0') THEN
			VER_COUNT<="0000000000";
		ELSE
			IF(CLK'EVENT AND CLK='1') THEN
				VER_COUNT<=VER_COUNT+1;
			END IF;
		END IF;
	END PROCESS;

------场计数器
	PROCESS(VERSYNC,COMSYNC)                           
	BEGIN
		IF(COMSYNC='0') THEN
		--	IF (DATABUS="000")THEN
				COM_REG_A<="0001000000";--DATA_IN;
		--	ELSIF(DATABUS="001")THEN
				COM_REG_B<="0001010100";--DATA_IN;
		--	ELSIF(DATABUS="010")THEN
				VER_REG_A<="0010000000";--DATA_IN;
		--	ELSIF(DATABUS="011")THEN
				VER_REG_B<="0111011100";--DATA_IN;
		--	END IF;
				COM_COUNT<="0000000000";
		ELSE
			IF(VERSYNC'EVENT AND VERSYNC='1') THEN
			   COM_COUNT<=COM_COUNT+1;
			END IF;
		END IF;
	END PROCESS;
	-------------------------------------------------

---------------------------------------------------------------------
	PROCESS(VER_REG_A,VER_REG_B,COM_REG_A,COM_REG_B,VER_COUNT,COM_COUNT)
	BEGIN
		IF((VER_REG_A<VER_COUNT AND VER_COUNT<VER_REG_B) AND (COM_REG_A<COM_COUNT AND COM_COUNT<COM_REG_B))THEN 
		    DETECTOUT<='1';
		ELSE
		 	DETECTOUT<='0';	
		END IF;
	END PROCESS;
END Control;