video.tan.rpt

在屏幕上形成矩形的VHDL程序

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+---------------------------+
; Timing Analyzer Messages  ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
    Info: Processing started: Fri Mar 07 18:49:06 2008
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off VIDEO -c VIDEO
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node CLK is an undefined clock
    Info: Assuming node VERSYNC is an undefined clock
Info: Clock CLK has Internal fmax of 76.92 MHz between source register lpm_counter:VER_COUNT_rtl_0|dffs[0] and destination register lpm_counter:VER_COUNT_rtl_0|dffs[9] (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 11; REG Node = 'lpm_counter:VER_COUNT_rtl_0|dffs[0]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC122; Fanout = 2; REG Node = 'lpm_counter:VER_COUNT_rtl_0|dffs[9]'
        Info: Total cell delay = 6.000 ns ( 75.00 % )
        Info: Total interconnect delay = 2.000 ns ( 25.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock CLK to destination register is 10.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_36; Fanout = 10; CLK Node = 'CLK'
            Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC122; Fanout = 2; REG Node = 'lpm_counter:VER_COUNT_rtl_0|dffs[9]'
            Info: Total cell delay = 8.000 ns ( 80.00 % )
            Info: Total interconnect delay = 2.000 ns ( 20.00 % )
        Info: - Longest clock path from clock CLK to source register is 10.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_36; Fanout = 10; CLK Node = 'CLK'
            Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC1; Fanout = 11; REG Node = 'lpm_counter:VER_COUNT_rtl_0|dffs[0]'
            Info: Total cell delay = 8.000 ns ( 80.00 % )
            Info: Total interconnect delay = 2.000 ns ( 20.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: Clock VERSYNC has Internal fmax of 76.92 MHz between source register lpm_counter:COM_COUNT_rtl_1|dffs[0] and destination register lpm_counter:COM_COUNT_rtl_1|dffs[9] (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 11; REG Node = 'lpm_counter:COM_COUNT_rtl_1|dffs[0]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC121; Fanout = 2; REG Node = 'lpm_counter:COM_COUNT_rtl_1|dffs[9]'
        Info: Total cell delay = 6.000 ns ( 75.00 % )
        Info: Total interconnect delay = 2.000 ns ( 25.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock VERSYNC to destination register is 10.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_77; Fanout = 10; CLK Node = 'VERSYNC'
            Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC121; Fanout = 2; REG Node = 'lpm_counter:COM_COUNT_rtl_1|dffs[9]'
            Info: Total cell delay = 8.000 ns ( 80.00 % )
            Info: Total interconnect delay = 2.000 ns ( 20.00 % )
        Info: - Longest clock path from clock VERSYNC to source register is 10.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_77; Fanout = 10; CLK Node = 'VERSYNC'
            Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC2; Fanout = 11; REG Node = 'lpm_counter:COM_COUNT_rtl_1|dffs[0]'
            Info: Total cell delay = 8.000 ns ( 80.00 % )
            Info: Total interconnect delay = 2.000 ns ( 20.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tco from clock CLK to destination pin DETECTOUT through register lpm_counter:VER_COUNT_rtl_0|dffs[0] is 26.000 ns
    Info: + Longest clock path from clock CLK to source register is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_36; Fanout = 10; CLK Node = 'CLK'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC1; Fanout = 11; REG Node = 'lpm_counter:VER_COUNT_rtl_0|dffs[0]'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 15.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 11; REG Node = 'lpm_counter:VER_COUNT_rtl_0|dffs[0]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC116; Fanout = 1; COMB Node = 'i134~14'
        Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC117; Fanout = 1; COMB Node = 'i134~18'
        Info: 4: + IC(0.000 ns) + CELL(2.000 ns) = 11.000 ns; Loc. = LC118; Fanout = 1; COMB Node = 'i134~9'
        Info: 5: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = Pin_75; Fanout = 0; PIN Node = 'DETECTOUT'
        Info: Total cell delay = 13.000 ns ( 86.67 % )
        Info: Total interconnect delay = 2.000 ns ( 13.33 % )
Info: Minimum tco from clock CLK to destination pin DETECTOUT through register lpm_counter:VER_COUNT_rtl_0|dffs[8] is 24.000 ns
    Info: + Shortest clock path from clock CLK to source register is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_36; Fanout = 10; CLK Node = 'CLK'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC124; Fanout = 6; REG Node = 'lpm_counter:VER_COUNT_rtl_0|dffs[8]'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Shortest register to pin delay is 13.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC124; Fanout = 6; REG Node = 'lpm_counter:VER_COUNT_rtl_0|dffs[8]'
        Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC118; Fanout = 1; COMB Node = 'i134~9'
        Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = Pin_75; Fanout = 0; PIN Node = 'DETECTOUT'
        Info: Total cell delay = 11.000 ns ( 84.62 % )
        Info: Total interconnect delay = 2.000 ns ( 15.38 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Mar 07 18:49:06 2008
    Info: Elapsed time: 00:00:00