📄 cd.rpt
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Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 2 8 8 8 8 6 8 8 8 8 8 8 6 1 1 8 8 7 0 8 4 8 8 1 7 8 8 0 8 8 2 8 8 1 8 1 8 223/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 8 8 8 3 8 8 7 7 8 8 8 6 7 8 4 8 8 2 0 5 8 6 5 7 8 7 8 7 8 8 3 8 8 1 8 8 8 245/0
D: 7 4 8 6 8 8 6 8 0 5 8 8 8 8 8 8 1 8 0 8 0 0 0 0 0 8 0 0 0 1 8 0 0 0 0 0 0 142/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 8 8 8 0 8 8 0 0 7 8 8 1 7 8 1 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 96/0
Total: 25 28 32 17 32 30 21 23 23 29 32 23 28 25 14 32 25 17 0 21 12 14 13 8 15 23 16 7 16 17 13 16 16 2 16 9 16 706/0
Device-Specific Information: d:\eda cunfang\edadianzhizuo\10k10 rom\led\cd.rpt
cd
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
125 - - - -- INPUT G ^ 0 0 0 0 CKDSP
54 - - - -- INPUT G ^ 0 0 0 19 CR
55 - - - -- INPUT G ^ 0 0 0 0 HZSEL
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\eda cunfang\edadianzhizuo\10k10 rom\led\cd.rpt
cd
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
101 - - A -- OUTPUT 0 1 0 0 AD0
100 - - A -- OUTPUT 0 1 0 0 AD1
102 - - A -- OUTPUT 0 1 0 0 AD2
7 - - A -- OUTPUT 0 1 0 0 AD3
95 - - C -- OUTPUT 0 1 0 0 L0
17 - - C -- OUTPUT 0 1 0 0 L1
96 - - C -- OUTPUT 0 1 0 0 L2
14 - - C -- OUTPUT 0 1 0 0 L3
18 - - C -- OUTPUT 0 1 0 0 L4
12 - - C -- OUTPUT 0 1 0 0 L5
13 - - C -- OUTPUT 0 1 0 0 L6
11 - - C -- OUTPUT 0 1 0 0 L7
132 - - - 26 OUTPUT 0 1 0 0 L8
19 - - D -- OUTPUT 0 1 0 0 L9
20 - - D -- OUTPUT 0 1 0 0 L10
89 - - D -- OUTPUT 0 1 0 0 L11
23 - - D -- OUTPUT 0 1 0 0 L12
22 - - D -- OUTPUT 0 1 0 0 L13
21 - - D -- OUTPUT 0 1 0 0 L14
41 - - - 31 OUTPUT 0 1 0 0 L15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\eda cunfang\edadianzhizuo\10k10 rom\led\cd.rpt
cd
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - F 16 DFFE + 0 3 0 10 |AND1:37|dou3 (|AND1:37|:7)
- 3 - F 03 DFFE + 0 3 0 11 |AND1:37|dou2 (|AND1:37|:8)
- 2 - F 03 DFFE + 0 2 0 12 |AND1:37|dou1 (|AND1:37|:9)
- 1 - F 03 DFFE + 0 1 0 43 |AND1:37|dou0 (|AND1:37|:10)
- 4 - F 03 OR2 ! 0 4 0 24 |AND1:37|:44
- 2 - A 17 AND2 0 2 0 24 |AND2:31|LPM_ADD_SUB:69|addcore:adder|:55
- 5 - A 32 DFFE + 0 3 1 15 |AND2:31|dou3 (|AND2:31|:7)
- 1 - A 32 DFFE + 0 2 1 23 |AND2:31|dou2 (|AND2:31|:8)
- 8 - A 17 DFFE + 0 2 1 10 |AND2:31|dou1 (|AND2:31|:9)
- 6 - C 29 DFFE + 0 0 1 30 |AND2:31|dou0 (|AND2:31|:10)
- 2 - A 32 OR2 ! 0 3 0 26 |AND2:31|:44
- 1 - A 02 OR2 s ! 0 3 0 13 |ROM:36|~8602~1
- 5 - A 34 AND2 0 2 0 1 |ROM:36|:8622
- 5 - A 17 OR2 s ! 0 2 0 16 |ROM:36|~8702~1
- 5 - A 02 OR2 s ! 0 2 0 18 |ROM:36|~8742~1
- 6 - A 34 OR2 ! 0 2 0 5 |ROM:36|:8762
- 4 - A 34 AND2 s 0 2 0 5 |ROM:36|~8782~1
- 1 - C 29 OR2 s ! 0 2 0 21 |ROM:36|~8822~1
- 4 - A 31 AND2 0 2 0 4 |ROM:36|:8822
- 2 - C 29 OR2 s 0 2 0 19 |ROM:36|~8842~1
- 2 - A 02 OR2 s 0 3 0 12 |ROM:36|~8902~1
- 6 - A 29 OR2 ! 0 2 0 3 |ROM:36|:8902
- 8 - A 29 AND2 0 2 0 4 |ROM:36|:8942
- 3 - A 24 OR2 s 0 3 0 5 |ROM:36|~8982~1
- 4 - F 16 AND2 s ! 0 4 0 24 |ROM:36|~9042~1
- 1 - A 24 OR2 ! 0 2 0 5 |ROM:36|:9042
- 5 - A 16 OR2 s 0 2 0 9 |ROM:36|~9062~1
- 3 - A 04 AND2 0 2 0 1 |ROM:36|:9062
- 1 - A 06 OR2 s 0 2 0 12 |ROM:36|~9082~1
- 5 - A 26 OR2 ! 0 2 0 1 |ROM:36|:9082
- 4 - D 10 OR2 s 0 2 0 13 |ROM:36|~9102~1
- 4 - D 03 OR2 s 0 2 0 15 |ROM:36|~9122~1
- 2 - A 25 AND2 0 2 0 7 |ROM:36|:9142
- 1 - A 23 AND2 0 2 0 5 |ROM:36|:9162
- 4 - A 25 AND2 s ! 0 3 0 5 |ROM:36|~9182~1
- 5 - A 25 OR2 ! 0 2 0 3 |ROM:36|:9202
- 8 - A 14 OR2 ! 0 2 0 3 |ROM:36|:9222
- 3 - A 12 OR2 ! 0 3 0 3 |ROM:36|:9242
- 6 - A 12 OR2 ! 0 3 0 5 |ROM:36|:9262
- 7 - A 12 OR2 ! 0 3 0 4 |ROM:36|:9282
- 8 - D 19 OR2 ! 0 3 0 3 |ROM:36|:9302
- 5 - F 16 OR2 s ! 0 3 0 19 |ROM:36|~9322~1
- 5 - D 19 OR2 ! 0 3 0 2 |ROM:36|:9322
- 1 - A 11 OR2 ! 0 2 0 1 |ROM:36|:9342
- 7 - C 16 OR2 ! 0 4 0 5 |ROM:36|:9362
- 4 - A 13 OR2 ! 0 4 0 5 |ROM:36|:9382
- 3 - A 06 OR2 ! 0 2 0 4 |ROM:36|:9402
- 2 - A 13 OR2 ! 0 4 0 2 |ROM:36|:9442
- 6 - C 22 OR2 ! 0 4 0 10 |ROM:36|:9462
- 5 - C 22 AND2 0 4 0 5 |ROM:36|:9482
- 5 - A 09 AND2 s 0 4 0 1 |ROM:36|~9487~1
- 7 - A 09 OR2 s 0 4 0 1 |ROM:36|~9487~2
- 5 - A 18 OR2 ! 0 3 0 2 |ROM:36|:9502
- 4 - A 03 OR2 ! 0 3 0 1 |ROM:36|:9522
- 7 - A 02 OR2 s 0 3 0 15 |ROM:36|~9582~1
- 6 - A 35 OR2 ! 0 2 0 5 |ROM:36|:9602
- 7 - A 01 OR2 ! 0 2 0 4 |ROM:36|:9622
- 8 - A 36 OR2 ! 0 2 0 5 |ROM:36|:9682
- 8 - A 16 OR2 ! 0 2 0 5 |ROM:36|:9702
- 6 - C 02 OR2 ! 0 2 0 4 |ROM:36|:9722
- 7 - F 03 OR2 s 0 4 0 30 |ROM:36|~9762~1
- 4 - A 33 OR2 ! 0 2 0 6 |ROM:36|:9782
- 2 - A 09 OR2 s 0 4 0 1 |ROM:36|~9807~1
- 6 - A 09 OR2 s 0 3 0 2 |ROM:36|~9807~2
- 3 - A 09 AND2 s 0 4 0 1 |ROM:36|~9807~3
- 8 - A 09 OR2 0 4 0 1 |ROM:36|:9807
- 7 - A 10 OR2 ! 0 2 0 1 |ROM:36|:9862
- 3 - C 17 AND2 0 3 0 10 |ROM:36|:9922
- 7 - D 18 OR2 s 0 4 0 2 |ROM:36|~9927~1
- 1 - A 09 OR2 0 4 0 1 |ROM:36|:9927
- 3 - D 06 OR2 ! 0 2 0 8 |ROM:36|:9982
- 5 - C 16 OR2 ! 0 4 0 2 |ROM:36|:10002
- 3 - F 06 OR2 ! 0 4 0 2 |ROM:36|:10022
- 6 - A 06 OR2 ! 0 2 0 6 |ROM:36|:10042
- 3 - D 10 OR2 ! 0 2 0 6 |ROM:36|:10062
- 3 - D 03 AND2 0 4 0 15 |ROM:36|:10082
- 6 - F 11 OR2 0 4 0 1 |ROM:36|:10085
- 4 - F 06 AND2 s 0 2 0 1 |ROM:36|~10087~1
- 5 - F 10 OR2 ! 0 4 0 9 |ROM:36|:10102
- 3 - F 10 OR2 ! 0 4 0 5 |ROM:36|:10122
- 8 - F 10 OR2 ! 0 3 0 3 |ROM:36|:10142
- 8 - F 03 OR2 s 0 3 0 15 |ROM:36|~10162~1
- 5 - F 03 OR2 ! 0 3 0 3 |ROM:36|:10162
- 1 - D 03 OR2 s 0 2 0 24 |ROM:36|~10182~1
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