uart_core.v

来自「FPGA Cycloneii 系列的」· Verilog 代码 · 共 200 行

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// Generated by Quartus II Version 7.1 (Build Build 156 04/30/2007)
// Created on Sat Jun 30 10:20:43 2007

//  Module Declaration
module uart_core
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	clk, reset_n, send, send_bus, parity, regs_out, new_data, parity_out, 
	overflow, send_over, recv, recv_bus, recv_error, sel_pv, sel_clk, reset_parts, 
	ce_parts, send_si, sel_si, reset_dt, sel_out
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input clk;
	input reset_n;
	input send;
	input [7:0] send_bus;
	input parity;
	input [7:0] regs_out;
	input new_data;
	input parity_out;
	input overflow;
	output send_over;
	output recv;
	output [7:0] recv_bus;
	output recv_error;
	output sel_pv;
	output sel_clk;
	output reset_parts;
	output ce_parts;
	output send_si;
	output sel_si;
	output reset_dt;
	output sel_out;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	reg [2:0]uart_state;
	reg [TOTAL_BIT-1:0]send_buf;
	reg [3:0]si_count;
	reg send_si;
	reg reset_parts;
	reg reset_dt;
	reg ce_parts;
	reg sel_si;
	reg sel_clk;
	reg sel_pv;
	reg sel_out;
	reg send_over;
	reg recv;
	reg [7:0]recv_bus;
	reg recv_error;
	
	parameter TOTAL_BIT=4'hc;
	parameter UART_IDLE=3'h0;
	parameter UART_LOAD=3'h1;
	parameter UART_SEND=3'h2;
	parameter UART_END_SEND=3'h3;
	parameter UART_RECV=3'h4;
	parameter UART_END_RECV=3'h5;	
	

	// serial data produce
	always@ (send_bus,parity)
		send_buf[TOTAL_BIT-1:0]<={2'b0,send_bus[7:0],parity,1'b1};
	always@ (reset_n or si_count)
		if(reset_n==1'b0)
			send_si<=1'b1;
		else
			send_si<=send_buf[si_count];
	//state implement
	always@ (posedge clk or negedge reset_n)
		if(reset_n==1'b0)
		//system reset
			begin
				reset_dt<=1'b0;
				reset_parts<=1'b0;
				ce_parts<=1'b0;
				sel_si<=1'b0;
				sel_clk<=1'b0;
				sel_pv<=1'b0;
				sel_out<=1'b0;
				send_over<=1'b0;
				recv<=1'b0;
				recv_error<=1'b0;
				recv_bus<=8'b0;
				uart_state<=UART_IDLE;
				si_count<=4'b0;
			end
		else case(uart_state)
			UART_IDLE:
				if(new_data==1'b1)
					begin
						reset_parts<=1'b0;
						ce_parts<=1'b0;
						sel_si<=1'b1;
						sel_clk<=1'b0;
						sel_out<=1'b0;
						sel_pv<=1'b1;
						uart_state<=UART_RECV;
					end
				else if(send==1'b1)
					begin
						reset_parts<=1'b0;
						ce_parts<=1'b0;
						sel_si<=1'b0;
						sel_clk<=1'b0;
						sel_out<=1'b0;
						sel_pv<=1'b0;
						si_count<=TOTAL_BIT-1;
						uart_state<=UART_LOAD;
					end
				else
					reset_dt<=1'b1;
			UART_LOAD:
				if(overflow==1'b1)
					begin
						reset_parts<=1'b0;
						ce_parts<=1'b0;
						sel_si<=1'b0;
						sel_clk<=1'b1;
						sel_out<=1'b0;
						sel_pv<=1'b0;
						uart_state<=UART_SEND;
					end
				else
					begin
						sel_clk<=1'b1;
						if(si_count!=0)
							si_count<=si_count-4'h1;
							reset_parts<=1'b1;
							ce_parts<=1'b1;
					end
			UART_SEND:
				begin
					sel_out<=1'b1;
					sel_clk<=1'b0;
					if(overflow==1'b1)
						begin
							send_over<=1'b1;
							uart_state<=UART_END_SEND;
						end
					else
						begin
							reset_parts<=1'b1;
							ce_parts<=1'b1;
						end
				end
			UART_END_SEND:
				begin
					ce_parts<=1'b0;
					reset_dt<=1'b0;
					send_over<=1'b0;
					uart_state<=UART_IDLE;
				end
			UART_RECV:
				if(overflow==1'b1)
					begin
						recv<=1'b1;
						recv_bus<=regs_out;
						recv_error<=1'b0;
						uart_state<=UART_END_RECV;
					end
				else
					begin
						reset_parts<=1'b1;
						ce_parts<=1'b1;
					end
			UART_END_RECV:
				begin
					if(parity_out!=parity)
						recv_error<=1'b1;
						ce_parts<=1'b0;
						reset_dt<=1'b0;
						recv<=1'b0;
						uart_state<=UART_IDLE;
				end
				default:;
			endcase
endmodule