serial_uart_top.qsf

来自「FPGA Cycloneii 系列的」· QSF 代码 · 共 92 行

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		serial_uart_top_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name DEVICE EP2C20F484C7
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name TOP_LEVEL_ENTITY serial_uart_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:02:23  JUNE 29, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 7.1
set_global_assignment -name BDF_FILE serial_uart_top.bdf
set_global_assignment -name BDF_FILE uart_top.bdf
set_global_assignment -name VERILOG_FILE switcher_bus.v
set_global_assignment -name VERILOG_FILE switcher.v
set_global_assignment -name VERILOG_FILE shift_reg.v
set_global_assignment -name VERILOG_FILE detector.v
set_global_assignment -name VERILOG_FILE parity_verifier.v
set_global_assignment -name VERILOG_FILE bd_generator.v
set_global_assignment -name VERILOG_FILE counter.v
set_global_assignment -name VERILOG_FILE uart_core.v
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name END_TIME "10 us"
set_global_assignment -name VECTOR_WAVEFORM_FILE serial_uart_top.vwf
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE serial_uart_top.vwf
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name VERILOG_FILE deal.v
set_location_assignment PIN_L1 -to clk
set_location_assignment PIN_D1 -to data_led_1[6]
set_location_assignment PIN_D2 -to data_led_1[5]
set_location_assignment PIN_G3 -to data_led_1[4]
set_location_assignment PIN_H4 -to data_led_1[3]
set_location_assignment PIN_H5 -to data_led_1[2]
set_location_assignment PIN_H6 -to data_led_1[1]
set_location_assignment PIN_E1 -to data_led_1[0]
set_location_assignment PIN_E2 -to data_led_2[6]
set_location_assignment PIN_F1 -to data_led_2[5]
set_location_assignment PIN_F2 -to data_led_2[4]
set_location_assignment PIN_H1 -to data_led_2[3]
set_location_assignment PIN_H2 -to data_led_2[2]
set_location_assignment PIN_J1 -to data_led_2[1]
set_location_assignment PIN_J2 -to data_led_2[0]
set_location_assignment PIN_F14 -to RXD
set_global_assignment -name VERILOG_FILE get.v
set_location_assignment PIN_F4 -to data_led_3[0]
set_location_assignment PIN_D5 -to data_led_3[1]
set_location_assignment PIN_D6 -to data_led_3[2]
set_location_assignment PIN_J4 -to data_led_3[3]
set_location_assignment PIN_L8 -to data_led_3[4]
set_location_assignment PIN_F3 -to data_led_3[5]
set_location_assignment PIN_D4 -to data_led_3[6]
set_location_assignment PIN_G5 -to data_led_4[0]
set_location_assignment PIN_G6 -to data_led_4[1]
set_location_assignment PIN_C2 -to data_led_4[2]
set_location_assignment PIN_C1 -to data_led_4[3]
set_location_assignment PIN_E3 -to data_led_4[4]
set_location_assignment PIN_E4 -to data_led_4[5]
set_location_assignment PIN_D3 -to data_led_4[6]
set_location_assignment PIN_R17 -to recv
set_global_assignment -name VERILOG_FILE instruc2main.v
set_global_assignment -name VERILOG_FILE deal1.v
set_location_assignment PIN_R20 -to dataout2[0]
set_location_assignment PIN_R19 -to dataout2[1]
set_location_assignment PIN_U19 -to dataout2[2]
set_location_assignment PIN_Y19 -to dataout2[3]
set_location_assignment PIN_T18 -to dataout2[4]
set_location_assignment PIN_V19 -to dataout2[5]
set_location_assignment PIN_Y18 -to dataout2[6]
set_location_assignment PIN_U18 -to dataout2[7]
set_global_assignment -name VERILOG_FILE dealx.v