get.v.bak

来自「FPGA Cycloneii 系列的」· BAK 代码 · 共 84 行

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// Generated by Quartus II Version 7.1 (Build Build 156 04/30/2007)
// Created on Thu Mar 27 15:08:15 2008

//  Module Declaration
module get
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	in_signal, datain, dataout1, dataout2, dataout3, dataout4, dataout5
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input in_signal;
	input [7:0] datain;
	output [7:0] dataout1;
	output [7:0] dataout2;
	output [7:0] dataout3;
	output [7:0] dataout4;
	output [7:0] dataout5;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	reg [7:0] dataout1;
	reg [7:0] dataout2;
	reg [7:0] dataout3;
	reg [7:0] dataout4;
	reg [7:0] dataout5;
	reg [2:0] count=3'b001;
	
	always @(negedge in_signal)
		begin
		case(count)
		1:
			if (datain==8'hff)
				begin
					dataout1<=datain;
					count<=count+1;
				end
		2:
			begin
				dataout2<=datain;
				count<=count+1;
			end
		3:
			begin
				dataout3<=datain;
				count<=count+1;
			end
		4:
			begin
				dataout4<=datain;
				count<=count+1;
			end
		5:
			begin
				dataout5<=datain;
				count<=1;
			end
		endcase
		end
			



endmodule