prev_cmp_serial_uart_top.map.qmsg

来自「FPGA Cycloneii 系列的」· QMSG 代码 · 共 151 行 · 第 1/5 页

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shift_reg uart_top:inst\|shift_reg:inst13 " "Info: Elaborating entity \"shift_reg\" for hierarchy \"uart_top:inst\|shift_reg:inst13\"" {  } { { "uart_top.bdf" "inst13" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/uart_top.bdf" { { 896 728 896 1048 "inst13" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bd_generator uart_top:inst\|bd_generator:inst5 " "Info: Elaborating entity \"bd_generator\" for hierarchy \"uart_top:inst\|bd_generator:inst5\"" {  } { { "uart_top.bdf" "inst5" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/uart_top.bdf" { { 616 32 176 752 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 bd_generator.v(57) " "Warning (10230): Verilog HDL assignment warning at bd_generator.v(57): truncated value with size 32 to match size of target (16)" {  } { { "bd_generator.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/bd_generator.v" 57 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 bd_generator.v(68) " "Warning (10230): Verilog HDL assignment warning at bd_generator.v(68): truncated value with size 32 to match size of target (16)" {  } { { "bd_generator.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/bd_generator.v" 68 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 bd_generator.v(71) " "Warning (10230): Verilog HDL assignment warning at bd_generator.v(71): truncated value with size 32 to match size of target (16)" {  } { { "bd_generator.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/bd_generator.v" 71 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter uart_top:inst\|counter:inst3 " "Info: Elaborating entity \"counter\" for hierarchy \"uart_top:inst\|counter:inst3\"" {  } { { "uart_top.bdf" "inst3" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/uart_top.bdf" { { 616 424 568 736 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "deal deal:inst2 " "Info: Elaborating entity \"deal\" for hierarchy \"deal:inst2\"" {  } { { "serial_uart_top.bdf" "inst2" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/serial_uart_top.bdf" { { 312 808 1000 408 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 deal.v(48) " "Warning (10230): Verilog HDL assignment warning at deal.v(48): truncated value with size 32 to match size of target (4)" {  } { { "deal.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/deal.v" 48 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruc2main instruc2main:inst6 " "Info: Elaborating entity \"instruc2main\" for hierarchy \"instruc2main:inst6\"" {  } { { "serial_uart_top.bdf" "inst6" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/serial_uart_top.bdf" { { 264 472 696 584 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "instruc2main.v(94) " "Warning (10270): Verilog HDL Case Statement warning at instruc2main.v(94): incomplete case statement has no default case item" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 94 0 0 } }  } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 instruc2main.v(129) " "Warning (10230): Verilog HDL assignment warning at instruc2main.v(129): truncated value with size 32 to match size of target (12)" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 129 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "instruc2main.v(82) " "Warning (10270): Verilog HDL Case Statement warning at instruc2main.v(82): incomplete case statement has no default case item" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 82 0 0 } }  } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "Lognormal instruc2main.v(79) " "Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable \"Lognormal\", which holds its previous value in one or more paths through the always construct" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "Rayleigh_MP instruc2main.v(79) " "Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable \"Rayleigh_MP\", which holds its previous value in one or more paths through the always construct" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "Row_dis_delay instruc2main.v(79) " "Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable \"Row_dis_delay\", which holds its previous value in one or more paths through the always construct" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "FIFO6_time instruc2main.v(79) " "Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable \"FIFO6_time\", which holds its previous value in one or more paths through the always construct" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "FIFO6_amp instruc2main.v(79) " "Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable \"FIFO6_amp\", which holds its previous value in one or more paths through the always construct" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "FIFO5_time instruc2main.v(79) " "Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable \"FIFO5_time\", which holds its previous value in one or more paths through the always construct" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "FIFO5_amp instruc2main.v(79) " "Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable \"FIFO5_amp\", which holds its previous value in one or more paths through the always construct" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "FIFO4_time instruc2main.v(79) " "Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable \"FIFO4_time\", which holds its previous value in one or more paths through the always construct" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "FIFO4_amp instruc2main.v(79) " "Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable \"FIFO4_amp\", which holds its previous value in one or more paths through the always construct" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "FIFO3_time instruc2main.v(79) " "Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable \"FIFO3_time\", which holds its previous value in one or more paths through the always construct" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "FIFO3_amp instruc2main.v(79) " "Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable \"FIFO3_amp\", which holds its previous value in one or more paths through the always construct" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "FIFO2_time instruc2main.v(79) " "Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable \"FIFO2_time\", which holds its previous value in one or more paths through the always construct" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "FIFO2_amp instruc2main.v(79) " "Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable \"FIFO2_amp\", which holds its previous value in one or more paths through the always construct" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "FIFO1_time instruc2main.v(79) " "Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable \"FIFO1_time\", which holds its previous value in one or more paths through the always construct" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "FIFO1_amp instruc2main.v(79) " "Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable \"FIFO1_amp\", which holds its previous value in one or more paths through the always construct" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "Gauss_P instruc2main.v(79) " "Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable \"Gauss_P\", which holds its previous value in one or more paths through the always construct" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "doppler_step instruc2main.v(79) " "Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable \"doppler_step\", which holds its previous value in one or more paths through the always construct" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "doppler_step\[0\] instruc2main.v(79) " "Info (10041): Inferred latch for \"doppler_step\[0\]\" at instruc2main.v(79)" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "doppler_step\[1\] instruc2main.v(79) " "Info (10041): Inferred latch for \"doppler_step\[1\]\" at instruc2main.v(79)" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}