counter_s.v

来自「FPGA Cycloneii 系列的」· Verilog 代码 · 共 51 行

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// Generated by Quartus II Version 7.1 (Build Build 156 04/30/2007)
// Created on Sat Dec 15 18:23:11 2007

//  Module Declaration
module counter
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	clk, dataout
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input clk;
	output [7:0] dataout;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	reg [23:0]temp=0;
	reg [7:0]dataout=0;
	always @(posedge clk)
		begin
			temp<=temp+1;
			if (temp==10000000)  //20'b11111111111111111111
				begin
				dataout<=dataout+1;
				temp<=0;
				end
			else
				dataout<=dataout;
		end

endmodule