serial_uart_top.tan.rpt

来自「FPGA Cycloneii 系列的」· RPT 代码 · 共 273 行 · 第 1/5 页

; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C20F484C7       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                 ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------+-------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                           ; To                                                    ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------+-------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 111.64 MHz ( period = 8.957 ns )                    ; uart_top:inst|counter:inst3|overflow           ; uart_top:inst|uart_core:inst|recv_bus[5]              ; clk        ; clk      ; None                        ; None                      ; 1.778 ns                ;
; N/A                                     ; 111.64 MHz ( period = 8.957 ns )                    ; uart_top:inst|counter:inst3|overflow           ; uart_top:inst|uart_core:inst|recv_bus[4]              ; clk        ; clk      ; None                        ; None                      ; 1.778 ns                ;
; N/A                                     ; 111.64 MHz ( period = 8.957 ns )                    ; uart_top:inst|counter:inst3|overflow           ; uart_top:inst|uart_core:inst|recv_bus[6]              ; clk        ; clk      ; None                        ; None                      ; 1.778 ns                ;
; N/A                                     ; 111.64 MHz ( period = 8.957 ns )                    ; uart_top:inst|counter:inst3|overflow           ; uart_top:inst|uart_core:inst|recv_bus[0]              ; clk        ; clk      ; None                        ; None                      ; 1.778 ns                ;
; N/A                                     ; 111.64 MHz ( period = 8.957 ns )                    ; uart_top:inst|counter:inst3|overflow           ; uart_top:inst|uart_core:inst|recv_bus[2]              ; clk        ; clk      ; None                        ; None                      ; 1.778 ns                ;
; N/A                                     ; 111.64 MHz ( period = 8.957 ns )                    ; uart_top:inst|counter:inst3|overflow           ; uart_top:inst|uart_core:inst|recv_bus[7]              ; clk        ; clk      ; None                        ; None                      ; 1.778 ns                ;
; N/A                                     ; 111.64 MHz ( period = 8.957 ns )                    ; uart_top:inst|counter:inst3|overflow           ; uart_top:inst|uart_core:inst|recv_bus[3]              ; clk        ; clk      ; None                        ; None                      ; 1.778 ns                ;
; N/A                                     ; 111.64 MHz ( period = 8.957 ns )                    ; uart_top:inst|counter:inst3|overflow           ; uart_top:inst|uart_core:inst|recv_bus[1]              ; clk        ; clk      ; None                        ; None                      ; 1.778 ns                ;
; N/A                                     ; 117.63 MHz ( period = 8.501 ns )                    ; uart_top:inst|counter:inst3|overflow           ; uart_top:inst|uart_core:inst|uart_state.UART_IDLE     ; clk        ; clk      ; None                        ; None                      ; 1.322 ns                ;
; N/A                                     ; 126.39 MHz ( period = 7.912 ns )                    ; uart_top:inst|counter:inst3|overflow           ; uart_top:inst|uart_core:inst|recv                     ; clk        ; clk      ; None                        ; None                      ; 1.159 ns                ;
; N/A                                     ; 126.44 MHz ( period = 7.909 ns )                    ; uart_top:inst|shift_reg:inst13|shift_out[3]    ; uart_top:inst|uart_core:inst|recv_bus[5]              ; clk        ; clk      ; None                        ; None                      ; 0.791 ns                ;
; N/A                                     ; 126.45 MHz ( period = 7.908 ns )                    ; uart_top:inst|shift_reg:inst13|shift_out[1]    ; uart_top:inst|uart_core:inst|recv_bus[7]              ; clk        ; clk      ; None                        ; None                      ; 0.790 ns                ;
; N/A                                     ; 126.45 MHz ( period = 7.908 ns )                    ; uart_top:inst|shift_reg:inst13|shift_out[5]    ; uart_top:inst|uart_core:inst|recv_bus[3]              ; clk        ; clk      ; None                        ; None                      ; 0.790 ns                ;
; N/A                                     ; 126.52 MHz ( period = 7.904 ns )                    ; uart_top:inst|shift_reg:inst13|shift_out[8]    ; uart_top:inst|uart_core:inst|recv_bus[0]              ; clk        ; clk      ; None                        ; None                      ; 0.786 ns                ;
; N/A                                     ; 126.53 MHz ( period = 7.903 ns )                    ; uart_top:inst|shift_reg:inst13|shift_out[6]    ; uart_top:inst|uart_core:inst|recv_bus[2]              ; clk        ; clk      ; None                        ; None                      ; 0.785 ns                ;
; N/A                                     ; 127.26 MHz ( period = 7.858 ns )                    ; uart_top:inst|counter:inst3|overflow           ; uart_top:inst|uart_core:inst|reset_parts              ; clk        ; clk      ; None                        ; None                      ; 0.679 ns                ;
; N/A                                     ; 127.29 MHz ( period = 7.856 ns )                    ; uart_top:inst|counter:inst3|overflow           ; uart_top:inst|uart_core:inst|ce_parts                 ; clk        ; clk      ; None                        ; None                      ; 0.677 ns                ;