uart_top.bdf

来自「FPGA Cycloneii 系列的」· BDF 代码 · 共 1,114 行 · 第 1/2 页

BDF
1,114 行
字号
12
		(pt 0 56)
		(bidir)
		(mapping "din2" "TXD_data" )
		(annotation_block (mapping)(rect 1248 592 1336 624))
	)
	(mapper
		(pt 48 0)
		(bidir)
		(mapping "sel" "sel_out" )
		(annotation_block (mapping)(rect 1416 472 1504 504))
	)
	(mapper
		(pt 120 40)
		(bidir)
		(mapping "dout" "TXD" )
		(annotation_block (mapping)(rect 1488 576 1576 608))
	)
)
(block
	(rect 728 896 896 1048)
	(text "shift_reg" (rect 5 5 55 19)(font "Arial" (font_size 8)))	(text "inst13" (rect 5 138 34 150)(font "Arial" ))	(block_io "clk" (input))
	(block_io "reset_n" (input))
	(block_io "din" (input))
	(block_io "dout" (output))
	(block_io "regs_out[7..0]" (output))
	(block_io "parity_out" (output))
	(mapper
		(pt 72 0)
		(bidir)
		(mapping "reset_n" "reset_parts" )
		(annotation_block (mapping)(rect 816 848 920 880))
	)
	(mapper
		(pt 32 0)
		(bidir)
		(mapping "regs_out[7..0]" "regs_out[7..0]" )
		(annotation_block (mapping)(rect 576 848 720 880))
	)
	(mapper
		(pt 0 56)
		(bidir)
		(mapping "clk" "clk_out" )
		(annotation_block (mapping)(rect 624 968 712 1000))
	)
	(mapper
		(pt 0 120)
		(bidir)
		(mapping "din" "data" )
		(annotation_block (mapping)(rect 624 1032 712 1064))
	)
	(mapper
		(pt 40 152)
		(bidir)
		(mapping "dout" "TXD_data" )
		(annotation_block (mapping)(rect 656 1088 744 1120))
	)
	(mapper
		(pt 72 152)
		(bidir)
		(mapping "parity_out" "parity_out" )
		(annotation_block (mapping)(rect 864 1080 968 1112))
	)
)
(block
	(rect 424 256 824 616)
	(text "uart_core" (rect 5 5 60 19)(font "Arial" (font_size 8)))	(text "inst" (rect 5 346 22 358)(font "Arial" ))	(block_io "clk" (input))
	(block_io "reset_n" (input))
	(block_io "send" (input))
	(block_io "send_bus[7..0]" (input))
	(block_io "parity" (input))
	(block_io "regs_out[7..0]" (input))
	(block_io "new_data" (input))
	(block_io "parity_out" (input))
	(block_io "overflow" (input))
	(block_io "send_over" (output))
	(block_io "recv" (output))
	(block_io "recv_bus[7..0]" (output))
	(block_io "recv_error" (output))
	(block_io "sel_pv" (output))
	(block_io "sel_clk" (output))
	(block_io "reset_parts" (output))
	(block_io "ce_parts" (output))
	(block_io "send_si" (output))
	(block_io "sel_si" (output))
	(block_io "reset_dt" (output))
	(block_io "sel_out" (output))
	(mapper
		(pt 48 0)
		(bidir)
		)
	(mapper
		(pt 112 0)
		(bidir)
		)
	(mapper
		(pt 312 0)
		(bidir)
		)
	(mapper
		(pt 392 0)
		(bidir)
		)
	(mapper
		(pt 80 0)
		(bidir)
		(mapping "send_bus[7..0]" "send_bus[7..0]" )
		(annotation_block (mapping)(rect 520 208 672 240))
	)
	(mapper
		(pt 352 0)
		(bidir)
		(mapping "recv_bus[7..0]" "recv_bus[7..0]" )
		(annotation_block (mapping)(rect 720 160 872 192))
	)
	(mapper
		(pt 160 360)
		(bidir)
		(mapping "overflow" "overflow" )
		(annotation_block (mapping)(rect 760 688 856 720))
	)
	(mapper
		(pt 0 240)
		(bidir)
		(mapping "sel_clk" "sel_clk" )
		(annotation_block (mapping)(rect 320 512 408 544))
	)
	(mapper
		(pt 280 360)
		(bidir)
		(mapping "send_si" "send_si" )
		(annotation_block (mapping)(rect 720 608 816 640))
	)
	(mapper
		(pt 312 360)
		(bidir)
		(mapping "regs_out[7..0]" "regs_out[7..0]" )
		(annotation_block (mapping)(rect 752 648 896 680))
	)
	(mapper
		(pt 344 360)
		(bidir)
		(mapping "sel_si" "sel_si" )
		(annotation_block (mapping)(rect 800 600 888 632))
	)
	(mapper
		(pt 400 200)
		(bidir)
		(mapping "reset_dt" "reset_dt" )
		(annotation_block (mapping)(rect 928 472 1024 504))
	)
	(mapper
		(pt 400 232)
		(bidir)
		(mapping "new_data" "new_data" )
		(annotation_block (mapping)(rect 928 504 1040 536))
	)
	(mapper
		(pt 400 272)
		(bidir)
		(mapping "sel_out" "sel_out" )
		(annotation_block (mapping)(rect 840 544 928 576))
	)
	(mapper
		(pt 0 312)
		(bidir)
		(mapping "parity_out" "parity_out" )
		(annotation_block (mapping)(rect 296 584 408 616))
	)
	(mapper
		(pt 400 40)
		(bidir)
		(mapping "sel_pv" "sel" )
		(annotation_block (mapping)(rect 920 256 1008 288))
	)
	(mapper
		(pt 0 80)
		(bidir)
		(mapping "reset_n" "reset_n" )
		(annotation_block (mapping)(rect 296 312 392 344))
	)
	(mapper
		(pt 400 96)
		(bidir)
		(mapping "parity" "parity" )
		(annotation_block (mapping)(rect 840 368 928 400))
	)
	(mapper
		(pt 0 40)
		(bidir)
		(mapping "clk" "clock_system" )
		(annotation_block (mapping)(rect 288 216 400 248))
	)
	(mapper
		(pt 0 112)
		(bidir)
		(mapping "ce_parts" "ce_parts" )
		(annotation_block (mapping)(rect 256 360 352 392))
	)
	(mapper
		(pt 0 152)
		(bidir)
		(mapping "reset_parts" "reset_parts" )
		(annotation_block (mapping)(rect 240 408 368 440))
	)
)
(connector
	(pt 472 136)
	(pt 472 256)
	(conduit)
)
(connector
	(pt 536 136)
	(pt 536 256)
	(conduit)
)
(connector
	(pt 736 256)
	(pt 736 144)
	(conduit)
)
(connector
	(pt 816 256)
	(pt 816 144)
	(conduit)
)
(connector
	(text "source[7..0]" (rect 1104 392 1163 404)(font "Arial" ))
	(pt 1144 408)
	(pt 1104 408)
	(bus)
)
(connector
	(pt 1104 368)
	(pt 1168 368)
	(conduit)
)
(connector
	(text "ce_parts,reset_parts" (rect 354 632 455 644)(font "Arial" ))
	(pt 344 648)
	(pt 424 648)
	(bus)
)
(connector
	(text "sel_clk" (rect 394 480 428 492)(font "Arial" ))
	(pt 424 496)
	(pt 384 496)
)
(connector
	(text "indicator" (rect 176 704 217 716)(font "Arial" ))
	(pt 176 720)
	(pt 200 720)
)
(connector
	(text "clock_system" (rect 288 280 357 292)(font "Arial" ))
	(pt 272 296)
	(pt 304 296)
)
(connector
	(text "clock_system" (rect 56 547 68 616)(font "Arial" )(vertical))
	(pt 72 552)
	(pt 72 616)
)
(connector
	(text "clk_out" (rect 554 936 589 948)(font "Arial" ))
	(pt 544 952)
	(pt 576 952)
)
(connector
	(text "clk_out" (rect 698 936 733 948)(font "Arial" ))
	(pt 728 952)
	(pt 688 952)
)
(connector
	(text "regs_out[7..0]" (rect 760 880 828 892)(font "Arial" ))
	(pt 760 896)
	(pt 760 848)
	(bus)
)
(connector
	(text "reset_parts" (rect 800 832 855 844)(font "Arial" ))
	(pt 800 848)
	(pt 800 896)
)
(connector
	(text "RXD" (rect 274 72 296 84)(font "Arial" ))
	(pt 264 88)
	(pt 296 88)
)
(connector
	(text "TXD" (rect 106 112 126 124)(font "Arial" ))
	(pt 160 128)
	(pt 96 128)
)
(connector
	(text "send_si" (rect 1032 840 1069 852)(font "Arial" ))
	(pt 1032 856)
	(pt 1032 904)
)
(connector
	(text "RXD" (rect 1080 840 1102 852)(font "Arial" ))
	(pt 1080 856)
	(pt 1080 904)
)
(connector
	(text "sel_si" (rect 946 920 974 932)(font "Arial" ))
	(pt 936 936)
	(pt 1000 936)
)
(connector
	(text "data" (rect 698 1000 719 1012)(font "Arial" ))
	(pt 688 1016)
	(pt 728 1016)
)
(connector
	(text "data" (rect 946 992 967 1004)(font "Arial" ))
	(pt 1000 1008)
	(pt 936 1008)
)
(connector
	(text "clock_system" (rect 954 640 1023 652)(font "Arial" ))
	(pt 944 656)
	(pt 1024 656)
)
(connector
	(text "RXD" (rect 954 680 976 692)(font "Arial" ))
	(pt 1024 696)
	(pt 944 696)
)
(connector
	(text "reset_dt" (rect 1080 536 1120 548)(font "Arial" ))
	(pt 1080 552)
	(pt 1080 616)
)
(connector
	(text "new_data" (rect 1186 656 1232 668)(font "Arial" ))
	(pt 1176 672)
	(pt 1216 672)
)
(connector
	(pt 1016 248)
	(pt 1016 296)
)
(connector
	(text "reset_dt" (rect 834 440 874 452)(font "Arial" ))
	(pt 824 456)
	(pt 888 456)
)
(connector
	(text "new_data" (rect 834 472 880 484)(font "Arial" ))
	(pt 824 488)
	(pt 888 488)
)
(connector
	(text "sel_out" (rect 834 512 869 524)(font "Arial" ))
	(pt 824 528)
	(pt 888 528)
)
(connector
	(text "TXD_data" (rect 1282 560 1329 572)(font "Arial" ))
	(pt 1272 576)
	(pt 1352 576)
)
(connector
	(pt 1304 504)
	(pt 1304 544)
)
(connector
	(text "VCC" (rect 1314 528 1337 540)(font "Arial" ))
	(pt 1304 544)
	(pt 1352 544)
)
(connector
	(text "sel_out" (rect 1400 448 1435 460)(font "Arial" ))
	(pt 1400 464)
	(pt 1400 520)
)
(connector
	(text "TXD" (rect 1482 544 1502 556)(font "Arial" ))
	(pt 1472 560)
	(pt 1528 560)
)
(connector
	(text "TXD_data" (rect 768 1032 815 1044)(font "Arial" ))
	(pt 768 1048)
	(pt 768 1080)
)
(connector
	(pt 584 648)
	(pt 584 616)
)
(connector
	(text "overflow" (rect 568 632 610 644)(font "Arial" ))
	(pt 568 648)
	(pt 584 648)
)
(connector
	(text "send_si" (rect 704 600 741 612)(font "Arial" ))
	(pt 704 616)
	(pt 704 680)
)
(connector
	(text "regs_out[7..0]" (rect 736 600 804 612)(font "Arial" ))
	(pt 736 616)
	(pt 736 680)
	(bus)
)
(connector
	(text "sel_si" (rect 768 600 796 612)(font "Arial" ))
	(pt 768 616)
	(pt 768 680)
)
(connector
	(text "parity_out" (rect 384 552 433 564)(font "Arial" ))
	(pt 424 568)
	(pt 384 568)
)
(connector
	(text "sel" (rect 834 280 848 292)(font "Arial" ))
	(pt 1016 296)
	(pt 824 296)
)
(connector
	(text "parity_out" (rect 800 1016 849 1028)(font "Arial" ))
	(pt 800 1048)
	(pt 800 1080)
)
(connector
	(text "send_bus[7..0]" (rect 504 144 577 156)(font "Arial" ))
	(pt 504 136)
	(pt 504 256)
	(bus)
)
(connector
	(text "send_bus[7..0]" (rect 882 136 955 148)(font "Arial" ))
	(pt 944 152)
	(pt 872 152)
	(bus)
)
(connector
	(text "recv_bus[7..0]" (rect 776 200 847 212)(font "Arial" ))
	(pt 776 144)
	(pt 776 256)
	(bus)
)
(connector
	(text "sel_clk" (rect 394 792 428 804)(font "Arial" ))
	(pt 384 808)
	(pt 424 808)
)
(connector
	(text "indicator" (rect 394 816 435 828)(font "Arial" ))
	(pt 384 832)
	(pt 424 832)
)
(connector
	(text "source[7..0]" (rect 1098 168 1157 180)(font "Arial" ))
	(pt 1088 184)
	(pt 1144 184)
	(bus)
)
(connector
	(text "recv_bus[7..0]" (rect 882 200 953 212)(font "Arial" ))
	(pt 944 216)
	(pt 872 216)
	(bus)
)
(connector
	(text "bd_clk" (rect 322 928 353 940)(font "Arial" ))
	(pt 312 944)
	(pt 424 944)
)
(connector
	(text "reset_n" (rect 282 320 318 332)(font "Arial" ))
	(pt 272 336)
	(pt 424 336)
)
(connector
	(text "sel_clk" (rect 394 912 428 924)(font "Arial" ))
	(pt 384 928)
	(pt 424 928)
)
(connector
	(text "parity" (rect 938 336 966 348)(font "Arial" ))
	(pt 952 352)
	(pt 928 352)
)
(connector
	(text "parity" (rect 834 336 862 348)(font "Arial" ))
	(pt 824 352)
	(pt 856 352)
)
(connector
	(text "clock_system" (rect 162 984 231 996)(font "Arial" ))
	(pt 152 1000)
	(pt 264 1000)
)
(connector
	(text "clock_inv" (rect 322 984 369 996)(font "Arial" ))
	(pt 312 1000)
	(pt 424 1000)
)
(connector
	(text "clock_system" (rect 122 840 191 852)(font "Arial" ))
	(pt 112 856)
	(pt 224 856)
)
(connector
	(text "clk_inv" (rect 282 840 317 852)(font "Arial" ))
	(pt 272 856)
	(pt 424 856)
)
(connector
	(text "clock_system" (rect 362 280 431 292)(font "Arial" ))
	(pt 424 296)
	(pt 352 296)
)
(connector
	(text "bd_clk" (rect 176 656 207 668)(font "Arial" ))
	(pt 176 672)
	(pt 200 672)
)
(connector
	(text "ce_parts" (rect 370 352 412 364)(font "Arial" ))
	(pt 424 368)
	(pt 360 368)
)
(connector
	(text "reset_parts" (rect 370 392 425 404)(font "Arial" ))
	(pt 424 408)
	(pt 360 408)
)
(connector
	(text "ce_parts" (rect 104 536 146 548)(font "Arial" ))
	(pt 104 552)
	(pt 104 616)
)
(connector
	(text "reset_parts" (rect 136 536 191 548)(font "Arial" ))
	(pt 136 552)
	(pt 136 616)
)
(connector
	(text "clk_counter" (rect 496 704 508 760)(font "Arial" )(vertical))
	(pt 512 768)
	(pt 512 736)
)
(connector
	(text "bd_clk" (rect 1394 760 1425 772)(font "Arial" ))
	(pt 1416 776)
	(pt 1384 776)
)
(connector
	(text "new_data" (rect 1386 720 1432 732)(font "Arial" ))
	(pt 1408 736)
	(pt 1376 736)
)
12

uart_top.bdf - 源码说明

本页面展示了「FPGA Cycloneii 系列的」中的 uart_top.bdf 源码文件，采用 BDF 编程语言编写，共 1,114 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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