parity_verifier.v

来自「FPGA Cycloneii 系列的」· Verilog 代码 · 共 51 行

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// Generated by Quartus II Version 7.1 (Build Build 156 04/30/2007)
// Created on Sat Jun 30 10:18:18 2007

//  Module Declaration
module parity_verifier
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	parity_rule, source, parity
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input parity_rule;
	input [7:0] source;
	output parity;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	parameter DATA_LENGTH=8;
	parameter PARITY_ODD=0;
	parameter PARITY_EVEN=1;
	
	reg parity;
	always@ (source or parity_rule)
		if(parity_rule==PARITY_EVEN)
			parity=source[7]^source[6]^source[5]^source[4]^source[3]^source[2]^source[1]^source[0];
		else if(parity_rule==PARITY_ODD)
			parity=!(source[7]^source[6]^source[5]^source[4]^source[3]^source[2]^source[1]^source[0]);



endmodule