serial_uart_top.tan.summary

来自「FPGA Cycloneii 系列的」· SUMMARY 代码 · 共 67 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.365 ns
From           : RXD
To             : uart_top:inst|detector:inst9|state
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 18.393 ns
From           : instruc2main:inst6|FIFO2_time[0]
To             : data_led_4[6]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.010 ns
From           : RXD
To             : uart_top:inst|shift_reg:inst13|shift_out[0]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 111.64 MHz ( period = 8.957 ns )
From           : uart_top:inst|counter:inst3|overflow
To             : uart_top:inst|uart_core:inst|recv_bus[1]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : uart_top:inst|uart_core:inst|ce_parts
To             : uart_top:inst|counter:inst3|overflow
From Clock     : clk
To Clock       : clk
Failed Paths   : 71

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 71

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