prev_cmp_serial_uart_top.qmsg

来自「FPGA Cycloneii 系列的」· QMSG 代码 · 共 151 行 · 第 1/5 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 28 17:15:16 2008 " "Info: Processing started: Fri Mar 28 17:15:16 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off serial_uart_top -c serial_uart_top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off serial_uart_top -c serial_uart_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "serial_uart_top.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file serial_uart_top.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 serial_uart_top " "Info: Found entity 1: serial_uart_top" {  } { { "serial_uart_top.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/serial_uart_top.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_top.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file uart_top.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 uart_top " "Info: Found entity 1: uart_top" {  } { { "uart_top.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/uart_top.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "switcher_bus.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file switcher_bus.v" { { "Info" "ISGN_ENTITY_NAME" "1 switcher_bus " "Info: Found entity 1: switcher_bus" {  } { { "switcher_bus.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/switcher_bus.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "switcher.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file switcher.v" { { "Info" "ISGN_ENTITY_NAME" "1 switcher " "Info: Found entity 1: switcher" {  } { { "switcher.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/switcher.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shift_reg.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file shift_reg.v" { { "Info" "ISGN_ENTITY_NAME" "1 shift_reg " "Info: Found entity 1: shift_reg" {  } { { "shift_reg.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/shift_reg.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "detector.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file detector.v" { { "Info" "ISGN_ENTITY_NAME" "1 detector " "Info: Found entity 1: detector" {  } { { "detector.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/detector.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "parity_verifier.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file parity_verifier.v" { { "Info" "ISGN_ENTITY_NAME" "1 parity_verifier " "Info: Found entity 1: parity_verifier" {  } { { "parity_verifier.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/parity_verifier.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bd_generator.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file bd_generator.v" { { "Info" "ISGN_ENTITY_NAME" "1 bd_generator " "Info: Found entity 1: bd_generator" {  } { { "bd_generator.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/bd_generator.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file counter.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" {  } { { "counter.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/counter.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_core.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file uart_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_core " "Info: Found entity 1: uart_core" {  } { { "uart_core.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/uart_core.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "deal.v(46) " "Warning (10268): Verilog HDL information at deal.v(46): Always Construct contains both blocking and non-blocking assignments" {  } { { "deal.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/deal.v" 46 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "deal.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file deal.v" { { "Info" "ISGN_ENTITY_NAME" "1 deal " "Info: Found entity 1: deal" {  } { { "deal.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/deal.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "get.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file get.v" { { "Info" "ISGN_ENTITY_NAME" "1 get " "Info: Found entity 1: get" {  } { { "get.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/get.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "instruc2main.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file instruc2main.v" { { "Info" "ISGN_ENTITY_NAME" "1 instruc2main " "Info: Found entity 1: instruc2main" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "deal1.v(46) " "Warning (10268): Verilog HDL information at deal1.v(46): Always Construct contains both blocking and non-blocking assignments" {  } { { "deal1.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/deal1.v" 46 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "deal1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file deal1.v" { { "Info" "ISGN_ENTITY_NAME" "1 deal1 " "Info: Found entity 1: deal1" {  } { { "deal1.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/deal1.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "dealx.v(42) " "Warning (10268): Verilog HDL information at dealx.v(42): Always Construct contains both blocking and non-blocking assignments" {  } { { "dealx.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/dealx.v" 42 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dealx.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dealx.v" { { "Info" "ISGN_ENTITY_NAME" "1 dealx " "Info: Found entity 1: dealx" {  } { { "dealx.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/dealx.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "serial_uart_top " "Info: Elaborating entity \"serial_uart_top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_top uart_top:inst " "Info: Elaborating entity \"uart_top\" for hierarchy \"uart_top:inst\"" {  } { { "serial_uart_top.bdf" "inst" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/serial_uart_top.bdf" { { -40 184 408 120 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "switcher uart_top:inst\|switcher:inst10 " "Info: Elaborating entity \"switcher\" for hierarchy \"uart_top:inst\|switcher:inst10\"" {  } { { "uart_top.bdf" "inst10" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/uart_top.bdf" { { 520 1352 1472 640 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_core uart_top:inst\|uart_core:inst " "Info: Elaborating entity \"uart_core\" for hierarchy \"uart_top:inst\|uart_core:inst\"" {  } { { "uart_top.bdf" "inst" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/uart_top.bdf" { { 256 424 824 616 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "send_buf uart_core.v(89) " "Warning (10235): Verilog HDL Always Construct warning at uart_core.v(89): variable \"send_buf\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "uart_core.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/uart_core.v" 89 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 uart_core.v(129) " "Warning (10230): Verilog HDL assignment warning at uart_core.v(129): truncated value with size 32 to match size of target (4)" {  } { { "uart_core.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/uart_core.v" 129 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "parity_verifier uart_top:inst\|parity_verifier:inst2 " "Info: Elaborating entity \"parity_verifier\" for hierarchy \"uart_top:inst\|parity_verifier:inst2\"" {  } { { "uart_top.bdf" "inst2" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/uart_top.bdf" { { 328 952 1104 432 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "parity parity_verifier.v(42) " "Warning (10240): Verilog HDL Always Construct warning at parity_verifier.v(42): inferring latch(es) for variable \"parity\", which holds its previous value in one or more paths through the always construct" {  } { { "parity_verifier.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/parity_verifier.v" 42 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "switcher_bus uart_top:inst\|switcher_bus:inst1 " "Info: Elaborating entity \"switcher_bus\" for hierarchy \"uart_top:inst\|switcher_bus:inst1\"" {  } { { "uart_top.bdf" "inst1" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/uart_top.bdf" { { 128 944 1088 248 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "detector uart_top:inst\|detector:inst9 " "Info: Elaborating entity \"detector\" for hierarchy \"uart_top:inst\|detector:inst9\"" {  } { { "uart_top.bdf" "inst9" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/uart_top.bdf" { { 616 1024 1176 736 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}