deal1.v.bak

FPGA Cycloneii 系列的

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// Generated by Quartus II Version 7.1 (Build Build 156 04/30/2007)
// Created on Sat Dec 15 17:04:34 2007

//  Module Declaration
module deal
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	datain, data_led_1, data_led_2
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	
	input [5:0] datain;

	output [6:0] data_led_1;
	output [6:0] data_led_2;

	
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
    reg [6:0] data_led_1;
	reg [6:0] data_led_2;
	
	reg [3:0] temp;
	
	always @(datain)
		begin
		temp=datain-(datain/16)*16;
		case(datain/16)
			4'b0000: data_led_1<=7'b1000000;
			4'b0001: data_led_1<=7'b1111001;
			4'b0010: data_led_1<=7'b0100100;
			4'b0011: data_led_1<=7'b0110000;
			4'b0100: data_led_1<=7'b0011001;
			4'b0101: data_led_1<=7'b0010010;
			4'b0110: data_led_1<=7'b0000010;
			4'b0111: data_led_1<=7'b1111000;
			4'b1000: data_led_1<=7'b0000000;
			4'b1001: data_led_1<=7'b0010000;
			4'b1010: data_led_1<=7'b0001000;
			4'b1011: data_led_1<=7'b0000011;
			4'b1100: data_led_1<=7'b1000110;
			4'b1101: data_led_1<=7'b0100001;
			4'b1110: data_led_1<=7'b0000110;
			4'b1111: data_led_1<=7'b0001110;
		endcase
		case(temp)
			4'b0000: data_led_2<=7'b1000000;
			4'b0001: data_led_2<=7'b1111001;
			4'b0010: data_led_2<=7'b0100100;
			4'b0011: data_led_2<=7'b0110000;
			4'b0100: data_led_2<=7'b0011001;
			4'b0101: data_led_2<=7'b0010010;
			4'b0110: data_led_2<=7'b0000010;
			4'b0111: data_led_2<=7'b1111000;
			4'b1000: data_led_2<=7'b0000000;
			4'b1001: data_led_2<=7'b0010000;
			4'b1010: data_led_2<=7'b0001000;
			4'b1011: data_led_2<=7'b0000011;
			4'b1100: data_led_2<=7'b1000110;
			4'b1101: data_led_2<=7'b0100001;
			4'b1110: data_led_2<=7'b0000110;
			4'b1111: data_led_2<=7'b0001110;
		endcase
		end
endmodule