serial_uart_top.map.smsg

来自「FPGA Cycloneii 系列的」· SMSG 代码 · 共 4 行

Warning (10268): Verilog HDL information at deal.v(46): Always Construct contains both blocking and non-blocking assignments
Warning (10268): Verilog HDL information at deal1.v(46): Always Construct contains both blocking and non-blocking assignments
Warning (10268): Verilog HDL information at dealx.v(42): Always Construct contains both blocking and non-blocking assignments