detector.v.bak

FPGA Cycloneii 系列的

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// Generated by Quartus II Version 7.1 (Build Build 156 04/30/2007)
// Created on Sat Jun 30 10:17:45 2007

//  Module Declaration
module detector
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	clk, reset_n, RXD, new_data
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input clk;
	input reset_n;
	input RXD;
	output new_data;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	reg state;
	reg new_data;
	parameter dt_unlock=1'b0;
	parameter dt_lock=1'b1;
	wire clk_inv;
	
	assign clk_inv=!clk;
	
	always@ (posedge clk_inv or negedge reset_n)
		if (reset_n==1'b0)
			begin
				state<=dt_unlock;
				new_data<=1'b0;
			end
		else if (state==dt_unlock && RXD==1'b0)
			begin
				state<=dt_lock;
				new_data<=1'b1;
			end
		else
			new_data<=1'b0;



endmodule