serial_uart_top.fit.rpt

FPGA Cycloneii 系列的

; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/serial_uart_top.pin.


+-------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                       ;
+---------------------------------------------+---------------------------------------+
; Resource                                    ; Usage                                 ;
+---------------------------------------------+---------------------------------------+
; Total logic elements                        ; 132 / 18,752 ( < 1 % )                ;
;     -- Combinational with no register       ; 52                                    ;
;     -- Register only                        ; 26                                    ;
;     -- Combinational with a register        ; 54                                    ;
;                                             ;                                       ;
; Logic element usage by number of LUT inputs ;                                       ;
;     -- 4 input functions                    ; 42                                    ;
;     -- 3 input functions                    ; 34                                    ;
;     -- <=2 input functions                  ; 30                                    ;
;     -- Register only                        ; 26                                    ;
;                                             ;                                       ;
; Logic elements by mode                      ;                                       ;
;     -- normal mode                          ; 88                                    ;
;     -- arithmetic mode                      ; 18                                    ;
;                                             ;                                       ;
; Total registers*                            ; 80 / 19,649 ( < 1 % )                 ;
;     -- Dedicated logic registers            ; 80 / 18,752 ( < 1 % )                 ;
;     -- I/O registers                        ; 0 / 897 ( 0 % )                       ;
;                                             ;                                       ;
; Total LABs:  partially or completely used   ; 14 / 1,172 ( 1 % )                    ;
; User inserted logic elements                ; 0                                     ;
; Virtual pins                                ; 0                                     ;
; I/O pins                                    ; 39 / 315 ( 12 % )                     ;
;     -- Clock pins                           ; 1 / 8 ( 13 % )                        ;
; Global signals                              ; 7                                     ;
; M4Ks                                        ; 0 / 52 ( 0 % )                        ;
; Total memory bits                           ; 0 / 239,616 ( 0 % )                   ;
; Total RAM block bits                        ; 0 / 239,616 ( 0 % )                   ;
; Embedded Multiplier 9-bit elements          ; 0 / 52 ( 0 % )                        ;
; PLLs                                        ; 0 / 4 ( 0 % )                         ;
; Global clocks                               ; 7 / 16 ( 44 % )                       ;
; Average interconnect usage                  ; 0%                                    ;
; Peak interconnect usage                     ; 1%                                    ;
; Maximum fan-out node                        ; clk~clkctrl                           ;
; Maximum fan-out                             ; 32                                    ;
; Highest non-global fan-out signal           ; uart_top:inst|uart_core:inst|ce_parts ;
; Highest non-global fan-out                  ; 24                                    ;
; Total fan-out                               ; 631                                   ;
; Average fan-out                             ; 2.50                                  ;
+---------------------------------------------+---------------------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                 ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; RXD  ; F14   ; 4        ; 35           ; 27           ; 2           ; 3                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;