sin_sample.tan.qmsg

EP2C CYCONLY 系列的FPGA时钟测试程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "inclk0 memory memory lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ug81:auto_generated\|ram_block1a0~porta_address_reg0 lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ug81:auto_generated\|q_a\[0\] 216.08 MHz Internal " "Info: Clock \"inclk0\" Internal fmax is restricted to 216.08 MHz between source memory \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ug81:auto_generated\|ram_block1a0~porta_address_reg0\" and destination memory \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ug81:auto_generated\|q_a\[0\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.314 ns 2.314 ns 4.628 ns " "Info: fmax restricted to Clock High delay (2.314 ns) plus Clock Low delay (2.314 ns) : restricted to 4.628 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.267 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.267 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ug81:auto_generated\|ram_block1a0~porta_address_reg0 1 MEM M4K_X41_Y20 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X41_Y20; Fanout = 14; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ug81:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_ug81.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_ug81.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.267 ns) 3.267 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ug81:auto_generated\|q_a\[0\] 2 MEM M4K_X41_Y20 1 " "Info: 2: + IC(0.000 ns) + CELL(3.267 ns) = 3.267 ns; Loc. = M4K_X41_Y20; Fanout = 1; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ug81:auto_generated\|q_a\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.267 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_ug81.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_ug81.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.267 ns ( 100.00 % ) " "Info: Total cell delay = 3.267 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.267 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.267 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 3.267ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.023 ns - Smallest " "Info: - Smallest clock skew is -0.023 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk0 destination 3.327 ns + Shortest memory " "Info: + Shortest clock path from clock \"inclk0\" to destination memory is 3.327 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns inclk0 1 CLK PIN_F20 24 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_F20; Fanout = 24; CLK Node = 'inclk0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclk0 } "NODE_NAME" } } { "sin_sample.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/sin_sample.bdf" { { 72 -264 -96 88 "inclk0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.739 ns) + CELL(0.724 ns) 3.327 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ug81:auto_generated\|q_a\[0\] 2 MEM M4K_X41_Y20 1 " "Info: 2: + IC(1.739 ns) + CELL(0.724 ns) = 3.327 ns; Loc. = M4K_X41_Y20; Fanout = 1; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ug81:auto_generated\|q_a\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.463 ns" { inclk0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_ug81.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_ug81.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.588 ns ( 47.73 % ) " "Info: Total cell delay = 1.588 ns ( 47.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.739 ns ( 52.27 % ) " "Info: Total interconnect delay = 1.739 ns ( 52.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.327 ns" { inclk0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.327 ns" { inclk0 inclk0~combout lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] } { 0.000ns 0.000ns 1.739ns } { 0.000ns 0.864ns 0.724ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk0 source 3.350 ns - Longest memory " "Info: - Longest clock path from clock \"inclk0\" to source memory is 3.350 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns inclk0 1 CLK PIN_F20 24 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_F20; Fanout = 24; CLK Node = 'inclk0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclk0 } "NODE_NAME" } } { "sin_sample.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/sin_sample.bdf" { { 72 -264 -96 88 "inclk0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.739 ns) + CELL(0.747 ns) 3.350 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ug81:auto_generated\|ram_block1a0~porta_address_reg0 2 MEM M4K_X41_Y20 14 " "Info: 2: + IC(1.739 ns) + CELL(0.747 ns) = 3.350 ns; Loc. = M4K_X41_Y20; Fanout = 14; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ug81:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.486 ns" { inclk0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_ug81.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_ug81.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.611 ns ( 48.09 % ) " "Info: Total cell delay = 1.611 ns ( 48.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.739 ns ( 51.91 % ) " "Info: Total interconnect delay = 1.739 ns ( 51.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.350 ns" { inclk0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.350 ns" { inclk0 inclk0~combout lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 1.739ns } { 0.000ns 0.864ns 0.747ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.327 ns" { inclk0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.327 ns" { inclk0 inclk0~combout lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] } { 0.000ns 0.000ns 1.739ns } { 0.000ns 0.864ns 0.724ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.350 ns" { inclk0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.350 ns" { inclk0 inclk0~combout lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 1.739ns } { 0.000ns 0.864ns 0.747ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.234 ns + " "Info: + Micro clock to output delay of source is 0.234 ns" {  } { { "db/altsyncram_ug81.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_ug81.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.040 ns + " "Info: + Micro setup delay of destination is 0.040 ns" {  } { { "db/altsyncram_ug81.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_ug81.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.267 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.267 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 3.267ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.327 ns" { inclk0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.327 ns" { inclk0 inclk0~combout lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] } { 0.000ns 0.000ns 1.739ns } { 0.000ns 0.864ns 0.724ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.350 ns" { inclk0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.350 ns" { inclk0 inclk0~combout lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 1.739ns } { 0.000ns 0.864ns 0.747ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] } { 0.000ns } { 0.098ns } "" } } { "db/altsyncram_ug81.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_ug81.tdf" 40 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "inclk0 data_da\[0\] lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ug81:auto_generated\|q_a\[0\] 9.791 ns memory " "Info: tco from clock \"inclk0\" to destination pin \"data_da\[0\]\" through memory \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ug81:auto_generated\|q_a\[0\]\" is 9.791 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk0 source 3.327 ns + Longest memory " "Info: + Longest clock path from clock \"inclk0\" to source memory is 3.327 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns inclk0 1 CLK PIN_F20 24 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_F20; Fanout = 24; CLK Node = 'inclk0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclk0 } "NODE_NAME" } } { "sin_sample.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/sin_sample.bdf" { { 72 -264 -96 88 "inclk0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.739 ns) + CELL(0.724 ns) 3.327 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ug81:auto_generated\|q_a\[0\] 2 MEM M4K_X41_Y20 1 " "Info: 2: + IC(1.739 ns) + CELL(0.724 ns) = 3.327 ns; Loc. = M4K_X41_Y20; Fanout = 1; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ug81:auto_generated\|q_a\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.463 ns" { inclk0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_ug81.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_ug81.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.588 ns ( 47.73 % ) " "Info: Total cell delay = 1.588 ns ( 47.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.739 ns ( 52.27 % ) " "Info: Total interconnect delay = 1.739 ns ( 52.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.327 ns" { inclk0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.327 ns" { inclk0 inclk0~combout lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] } { 0.000ns 0.000ns 1.739ns } { 0.000ns 0.864ns 0.724ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.234 ns + " "Info: + Micro clock to output delay of source is 0.234 ns" {  } { { "db/altsyncram_ug81.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_ug81.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.230 ns + Longest memory pin " "Info: + Longest memory to pin delay is 6.230 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.098 ns) 0.098 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ug81:auto_generated\|q_a\[0\] 1 MEM M4K_X41_Y20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.098 ns) = 0.098 ns; Loc. = M4K_X41_Y20; Fanout = 1; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ug81:auto_generated\|q_a\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_ug81.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_ug81.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.312 ns) + CELL(2.820 ns) 6.230 ns data_da\[0\] 2 PIN PIN_P18 0 " "Info: 2: + IC(3.312 ns) + CELL(2.820 ns) = 6.230 ns; Loc. = PIN_P18; Fanout = 0; PIN Node = 'data_da\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.132 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] data_da[0] } "NODE_NAME" } } { "sin_sample.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/sin_sample.bdf" { { 80 728 904 96 "data_da\[13..0\]" "" } { 88 656 716 160 "data_da\[13..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.918 ns ( 46.84 % ) " "Info: Total cell delay = 2.918 ns ( 46.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.312 ns ( 53.16 % ) " "Info: Total interconnect delay = 3.312 ns ( 53.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.230 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] data_da[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.230 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] data_da[0] } { 0.000ns 3.312ns } { 0.098ns 2.820ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.327 ns" { inclk0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.327 ns" { inclk0 inclk0~combout lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] } { 0.000ns 0.000ns 1.739ns } { 0.000ns 0.864ns 0.724ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.230 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] data_da[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.230 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] data_da[0] } { 0.000ns 3.312ns } { 0.098ns 2.820ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "110 " "Info: Allocated 110 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 24 14:40:58 2008 " "Info: Processing ended: Mon Mar 24 14:40:58 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}