sin_sample.fit.rpt

EP2C CYCONLY 系列的FPGA时钟测试程序

; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/sin_sample.pin.


+-----------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                                                                     ;
+---------------------------------------------+-------------------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                               ;
+---------------------------------------------+-------------------------------------------------------------------------------------+
; Total logic elements                        ; 5 / 18,752 ( < 1 % )                                                                ;
;     -- Combinational with no register       ; 0                                                                                   ;
;     -- Register only                        ; 0                                                                                   ;
;     -- Combinational with a register        ; 5                                                                                   ;
;                                             ;                                                                                     ;
; Logic element usage by number of LUT inputs ;                                                                                     ;
;     -- 4 input functions                    ; 0                                                                                   ;
;     -- 3 input functions                    ; 1                                                                                   ;
;     -- <=2 input functions                  ; 4                                                                                   ;
;     -- Register only                        ; 0                                                                                   ;
;                                             ;                                                                                     ;
; Logic elements by mode                      ;                                                                                     ;
;     -- normal mode                          ; 2                                                                                   ;
;     -- arithmetic mode                      ; 3                                                                                   ;
;                                             ;                                                                                     ;
; Total registers*                            ; 5 / 19,649 ( < 1 % )                                                                ;
;     -- Dedicated logic registers            ; 5 / 18,752 ( < 1 % )                                                                ;
;     -- I/O registers                        ; 0 / 897 ( 0 % )                                                                     ;
;                                             ;                                                                                     ;
; Total LABs:  partially or completely used   ; 1 / 1,172 ( < 1 % )                                                                 ;
; User inserted logic elements                ; 0                                                                                   ;
; Virtual pins                                ; 0                                                                                   ;
; I/O pins                                    ; 15 / 315 ( 5 % )                                                                    ;
;     -- Clock pins                           ; 0 / 8 ( 0 % )                                                                       ;
; Global signals                              ; 0                                                                                   ;
; M4Ks                                        ; 1 / 52 ( 2 % )                                                                      ;
; Total memory bits                           ; 448 / 239,616 ( < 1 % )                                                             ;
; Total RAM block bits                        ; 4,608 / 239,616 ( 2 % )                                                             ;
; Embedded Multiplier 9-bit elements          ; 0 / 52 ( 0 % )                                                                      ;
; PLLs                                        ; 0 / 4 ( 0 % )                                                                       ;
; Global clocks                               ; 0 / 16 ( 0 % )                                                                      ;
; Average interconnect usage                  ; 0%                                                                                  ;
; Peak interconnect usage                     ; 0%                                                                                  ;
; Maximum fan-out node                        ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0] ;
; Maximum fan-out                             ; 14                                                                                  ;
; Highest non-global fan-out signal           ; inclk0                                                                              ;
; Highest non-global fan-out                  ; 6                                                                                   ;
; Total fan-out                               ; 39                                                                                  ;
; Average fan-out                             ; 1.34                                                                                ;
+---------------------------------------------+-------------------------------------------------------------------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                   ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name   ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; inclk0 ; F20   ; 5        ; 50           ; 23           ; 0           ; 6                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+