ad_da.v

来自「EP2C CYCONLY 系列的FPGA时钟测试程序」· Verilog 代码 · 共 62 行

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// Generated by Quartus II Version 7.1 (Build Build 156 04/30/2007)
// Created on Fri Mar 21 14:23:48 2008

//  Module Declaration
module ad_da
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	clk_da, data_in, data_out
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input clk_da;
	input [11:0] data_in;
	output [11:0] data_out;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

//	reg [11:0]temp;
//	reg [11:0]temp_da;
	reg [11:0]data_out;
	
	always @(posedge clk_da)
		begin
			if (data_in>=0 & data_in<2048)
				data_out<=data_in+2048;
			else if (data_in>=2048 & data_in<4096)
				data_out<=data_in-2048;
		end
//	always @(posedge clk_da)
//		begin 
//			data_da<=temp_da;
//		end








endmodule