sin_sample.sim.rpt

EP2C CYCONLY 系列的FPGA时钟测试程序

The following table displays output ports that toggle between 1 and 0 during simulation.
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; Complete 1/0-Value Coverage                                                                                                                                                                                                                                                         ;
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; Node Name                                                                                                                         ; Output Port Name                                                                                                             ; Output Port Type ;
+-----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+------------------+
; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0 ; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[0]  ; portadataout0    ;
; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0 ; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[1]  ; portadataout1    ;
; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0 ; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[2]  ; portadataout2    ;
; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0 ; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[3]  ; portadataout3    ;
; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0 ; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[4]  ; portadataout4    ;
; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0 ; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[5]  ; portadataout5    ;
; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0 ; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[6]  ; portadataout6    ;
; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0 ; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[7]  ; portadataout7    ;
; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0 ; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[8]  ; portadataout8    ;
; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0 ; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[9]  ; portadataout9    ;
; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0 ; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[10] ; portadataout10   ;
; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0 ; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[11] ; portadataout11   ;
; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0 ; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[12] ; portadataout12   ;
; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0 ; |sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[13] ; portadataout13   ;
; |sin_sample|address_gen:inst1|address[1]                                                                                          ; |sin_sample|address_gen:inst1|address[1]                                                                                     ; regout           ;
; |sin_sample|address_gen:inst1|address[2]                                                                                          ; |sin_sample|address_gen:inst1|address[2]                                                                                     ; regout           ;
; |sin_sample|address_gen:inst1|address[3]                                                                                          ; |sin_sample|address_gen:inst1|address[3]                                                                                     ; regout           ;
; |sin_sample|address_gen:inst1|address[4]                                                                                          ; |sin_sample|address_gen:inst1|address[4]                                                                                     ; regout           ;
; |sin_sample|address_gen:inst1|address[1]~18                                                                                       ; |sin_sample|address_gen:inst1|address[1]~18                                                                                  ; combout          ;
; |sin_sample|address_gen:inst1|address[1]~18                                                                                       ; |sin_sample|address_gen:inst1|address[1]~22                                                                                  ; cout             ;
; |sin_sample|address_gen:inst1|address[2]~19                                                                                       ; |sin_sample|address_gen:inst1|address[2]~19                                                                                  ; combout          ;
; |sin_sample|address_gen:inst1|address[2]~19                                                                                       ; |sin_sample|address_gen:inst1|address[2]~23                                                                                  ; cout             ;
; |sin_sample|address_gen:inst1|address[3]~20                                                                                       ; |sin_sample|address_gen:inst1|address[3]~20                                                                                  ; combout          ;
; |sin_sample|address_gen:inst1|address[3]~20                                                                                       ; |sin_sample|address_gen:inst1|address[3]~24                                                                                  ; cout             ;
; |sin_sample|address_gen:inst1|address[4]~21                                                                                       ; |sin_sample|address_gen:inst1|address[4]~21                                                                                  ; combout          ;
; |sin_sample|address_gen:inst1|address[0]                                                                                          ; |sin_sample|address_gen:inst1|address[0]                                                                                     ; regout           ;
; |sin_sample|address_gen:inst1|address[0]~26                                                                                       ; |sin_sample|address_gen:inst1|address[0]~26                                                                                  ; combout          ;
; |sin_sample|data_ad[13]                                                                                                           ; |sin_sample|data_ad[13]                                                                                                      ; padio            ;
; |sin_sample|data_ad[12]                                                                                                           ; |sin_sample|data_ad[12]                                                                                                      ; padio            ;
; |sin_sample|data_ad[11]                                                                                                           ; |sin_sample|data_ad[11]                                                                                                      ; padio            ;
; |sin_sample|data_ad[10]                                                                                                           ; |sin_sample|data_ad[10]                                                                                                      ; padio            ;
; |sin_sample|data_ad[9]                                                                                                            ; |sin_sample|data_ad[9]                                                                                                       ; padio            ;
; |sin_sample|data_ad[8]                                                                                                            ; |sin_sample|data_ad[8]                                                                                                       ; padio            ;
; |sin_sample|data_ad[7]                                                                                                            ; |sin_sample|data_ad[7]                                                                                                       ; padio            ;
; |sin_sample|data_ad[6]                                                                                                            ; |sin_sample|data_ad[6]                                                                                                       ; padio            ;
; |sin_sample|data_ad[5]                                                                                                            ; |sin_sample|data_ad[5]                                                                                                       ; padio            ;
; |sin_sample|data_ad[4]                                                                                                            ; |sin_sample|data_ad[4]                                                                                                       ; padio            ;
; |sin_sample|data_ad[3]                                                                                                            ; |sin_sample|data_ad[3]                                                                                                       ; padio            ;
; |sin_sample|data_ad[2]                                                                                                            ; |sin_sample|data_ad[2]                                                                                                       ; padio            ;
; |sin_sample|data_ad[1]                                                                                                            ; |sin_sample|data_ad[1]                                                                                                       ; padio            ;
; |sin_sample|data_ad[0]                                                                                                            ; |sin_sample|data_ad[0]                                                                                                       ; padio            ;
; |sin_sample|data_da[13]                                                                                                           ; |sin_sample|data_da[13]                                                                                                      ; padio            ;
; |sin_sample|data_da[12]                                                                                                           ; |sin_sample|data_da[12]                                                                                                      ; padio            ;
; |sin_sample|data_da[11]                                                                                                           ; |sin_sample|data_da[11]                                                                                                      ; padio            ;
; |sin_sample|data_da[10]                                                                                                           ; |sin_sample|data_da[10]                                                                                                      ; padio            ;
; |sin_sample|data_da[9]                                                                                                            ; |sin_sample|data_da[9]                                                                                                       ; padio            ;
; |sin_sample|data_da[8]                                                                                                            ; |sin_sample|data_da[8]                                                                                                       ; padio            ;
; |sin_sample|data_da[7]                                                                                                            ; |sin_sample|data_da[7]                                                                                                       ; padio            ;
; |sin_sample|data_da[6]                                                                                                            ; |sin_sample|data_da[6]                                                                                                       ; padio            ;
; |sin_sample|data_da[5]                                                                                                            ; |sin_sample|data_da[5]                                                                                                       ; padio            ;
; |sin_sample|data_da[4]                                                                                                            ; |sin_sample|data_da[4]                                                                                                       ; padio            ;