sin_sample.tan.rpt

EP2C CYCONLY 系列的FPGA时钟测试程序

; N/A   ; None         ; 8.597 ns   ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[10] ; data_da[10] ; inclk0     ;
; N/A   ; None         ; 8.576 ns   ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[13] ; data_da[13] ; inclk0     ;
; N/A   ; None         ; 8.531 ns   ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[4]  ; data_da[4]  ; inclk0     ;
; N/A   ; None         ; 8.503 ns   ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[5]  ; data_da[5]  ; inclk0     ;
; N/A   ; None         ; 8.117 ns   ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[12] ; data_da[12] ; inclk0     ;
; N/A   ; None         ; 8.113 ns   ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[7]  ; data_da[7]  ; inclk0     ;
; N/A   ; None         ; 8.083 ns   ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[11] ; data_da[11] ; inclk0     ;
; N/A   ; None         ; 8.047 ns   ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[9]  ; data_da[9]  ; inclk0     ;
; N/A   ; None         ; 7.819 ns   ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[6]  ; data_da[6]  ; inclk0     ;
; N/A   ; None         ; 7.708 ns   ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[8]  ; data_da[8]  ; inclk0     ;
+-------+--------------+------------+--------------------------------------------------------------------------------------+-------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Mon Mar 24 14:40:56 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sin_sample -c sin_sample --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "inclk0" is an undefined clock
Info: Clock "inclk0" Internal fmax is restricted to 216.08 MHz between source memory "lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0" and destination memory "lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0]"
    Info: fmax restricted to Clock High delay (2.314 ns) plus Clock Low delay (2.314 ns) : restricted to 4.628 ns. Expand message to see actual delay path.
        Info: + Longest memory to memory delay is 3.267 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X41_Y20; Fanout = 14; MEM Node = 'lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0'
            Info: 2: + IC(0.000 ns) + CELL(3.267 ns) = 3.267 ns; Loc. = M4K_X41_Y20; Fanout = 1; MEM Node = 'lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0]'
            Info: Total cell delay = 3.267 ns ( 100.00 % )
        Info: - Smallest clock skew is -0.023 ns
            Info: + Shortest clock path from clock "inclk0" to destination memory is 3.327 ns
                Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_F20; Fanout = 24; CLK Node = 'inclk0'
                Info: 2: + IC(1.739 ns) + CELL(0.724 ns) = 3.327 ns; Loc. = M4K_X41_Y20; Fanout = 1; MEM Node = 'lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0]'
                Info: Total cell delay = 1.588 ns ( 47.73 % )
                Info: Total interconnect delay = 1.739 ns ( 52.27 % )
            Info: - Longest clock path from clock "inclk0" to source memory is 3.350 ns
                Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_F20; Fanout = 24; CLK Node = 'inclk0'
                Info: 2: + IC(1.739 ns) + CELL(0.747 ns) = 3.350 ns; Loc. = M4K_X41_Y20; Fanout = 14; MEM Node = 'lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0'
                Info: Total cell delay = 1.611 ns ( 48.09 % )
                Info: Total interconnect delay = 1.739 ns ( 51.91 % )
        Info: + Micro clock to output delay of source is 0.234 ns
        Info: + Micro setup delay of destination is 0.040 ns
Info: tco from clock "inclk0" to destination pin "data_da[0]" through memory "lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0]" is 9.791 ns
    Info: + Longest clock path from clock "inclk0" to source memory is 3.327 ns
        Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_F20; Fanout = 24; CLK Node = 'inclk0'
        Info: 2: + IC(1.739 ns) + CELL(0.724 ns) = 3.327 ns; Loc. = M4K_X41_Y20; Fanout = 1; MEM Node = 'lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0]'
        Info: Total cell delay = 1.588 ns ( 47.73 % )
        Info: Total interconnect delay = 1.739 ns ( 52.27 % )
    Info: + Micro clock to output delay of source is 0.234 ns
    Info: + Longest memory to pin delay is 6.230 ns
        Info: 1: + IC(0.000 ns) + CELL(0.098 ns) = 0.098 ns; Loc. = M4K_X41_Y20; Fanout = 1; MEM Node = 'lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0]'
        Info: 2: + IC(3.312 ns) + CELL(2.820 ns) = 6.230 ns; Loc. = PIN_P18; Fanout = 0; PIN Node = 'data_da[0]'
        Info: Total cell delay = 2.918 ns ( 46.84 % )
        Info: Total interconnect delay = 3.312 ns ( 53.16 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 110 megabytes of memory during processing
    Info: Processing ended: Mon Mar 24 14:40:58 2008
    Info: Elapsed time: 00:00:02