sin_sample.tan.rpt

EP2C CYCONLY 系列的FPGA时钟测试程序

; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; inclk0          ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'inclk0'                                                                                                                                                                                                                                                                                                                                                                            ;
+-------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                                                         ; To                                                                                                           ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg1 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg2 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg3 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg4 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[0]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[1]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg1 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[1]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg2 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[1]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg3 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[1]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg4 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[1]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[2]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg1 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[2]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg2 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[2]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg3 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[2]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg4 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[2]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[3]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg1 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[3]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg2 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[3]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg3 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[3]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg4 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[3]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[4]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg1 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[4]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg2 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[4]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg3 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[4]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg4 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[4]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[5]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg1 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[5]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg2 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[5]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg3 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[5]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg4 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[5]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[6]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg1 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[6]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg2 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[6]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg3 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[6]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg4 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[6]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg0 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[7]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg1 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[7]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg2 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[7]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;
; N/A   ; Restricted to 216.08 MHz ( period = 4.628 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|ram_block1a0~porta_address_reg3 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated|q_a[7]                          ; inclk0     ; inclk0   ; None                        ; None                      ; 3.267 ns                ;