sin_sample.map.rpt

EP2C CYCONLY 系列的FPGA时钟测试程序

; Assignment                      ; Value              ; From ; To                                    ;
+---------------------------------+--------------------+------+---------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                     ;
+---------------------------------+--------------------+------+---------------------------------------+


+--------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_rom0:inst|altsyncram:altsyncram_component ;
+------------------------------------+--------------------------------+----------------------+
; Parameter Name                     ; Value                          ; Type                 ;
+------------------------------------+--------------------------------+----------------------+
; BYTE_SIZE_BLOCK                    ; 8                              ; Untyped              ;
; AUTO_CARRY_CHAINS                  ; ON                             ; AUTO_CARRY           ;
; IGNORE_CARRY_BUFFERS               ; OFF                            ; IGNORE_CARRY         ;
; AUTO_CASCADE_CHAINS                ; ON                             ; AUTO_CASCADE         ;
; IGNORE_CASCADE_BUFFERS             ; OFF                            ; IGNORE_CASCADE       ;
; WIDTH_BYTEENA                      ; 1                              ; Untyped              ;
; OPERATION_MODE                     ; ROM                            ; Untyped              ;
; WIDTH_A                            ; 14                             ; Signed Integer       ;
; WIDTHAD_A                          ; 5                              ; Signed Integer       ;
; NUMWORDS_A                         ; 32                             ; Signed Integer       ;
; OUTDATA_REG_A                      ; CLOCK0                         ; Untyped              ;
; ADDRESS_ACLR_A                     ; NONE                           ; Untyped              ;
; OUTDATA_ACLR_A                     ; NONE                           ; Untyped              ;
; WRCONTROL_ACLR_A                   ; NONE                           ; Untyped              ;
; INDATA_ACLR_A                      ; NONE                           ; Untyped              ;
; BYTEENA_ACLR_A                     ; NONE                           ; Untyped              ;
; WIDTH_B                            ; 1                              ; Untyped              ;
; WIDTHAD_B                          ; 1                              ; Untyped              ;
; NUMWORDS_B                         ; 1                              ; Untyped              ;
; INDATA_REG_B                       ; CLOCK1                         ; Untyped              ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                         ; Untyped              ;
; RDCONTROL_REG_B                    ; CLOCK1                         ; Untyped              ;
; ADDRESS_REG_B                      ; CLOCK1                         ; Untyped              ;
; OUTDATA_REG_B                      ; UNREGISTERED                   ; Untyped              ;
; BYTEENA_REG_B                      ; CLOCK1                         ; Untyped              ;
; INDATA_ACLR_B                      ; NONE                           ; Untyped              ;
; WRCONTROL_ACLR_B                   ; NONE                           ; Untyped              ;
; ADDRESS_ACLR_B                     ; NONE                           ; Untyped              ;
; OUTDATA_ACLR_B                     ; NONE                           ; Untyped              ;
; RDCONTROL_ACLR_B                   ; NONE                           ; Untyped              ;
; BYTEENA_ACLR_B                     ; NONE                           ; Untyped              ;
; WIDTH_BYTEENA_A                    ; 1                              ; Signed Integer       ;
; WIDTH_BYTEENA_B                    ; 1                              ; Untyped              ;
; RAM_BLOCK_TYPE                     ; AUTO                           ; Untyped              ;
; BYTE_SIZE                          ; 8                              ; Untyped              ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                      ; Untyped              ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ           ; Untyped              ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ           ; Untyped              ;
; INIT_FILE                          ; ../../sin_gen14/sin_70_gen.mif ; Untyped              ;
; INIT_FILE_LAYOUT                   ; PORT_A                         ; Untyped              ;
; MAXIMUM_DEPTH                      ; 0                              ; Untyped              ;
; CLOCK_ENABLE_INPUT_A               ; BYPASS                         ; Untyped              ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                         ; Untyped              ;
; CLOCK_ENABLE_OUTPUT_A              ; BYPASS                         ; Untyped              ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                         ; Untyped              ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN                ; Untyped              ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN                ; Untyped              ;
; ENABLE_ECC                         ; FALSE                          ; Untyped              ;
; DEVICE_FAMILY                      ; Cyclone II                     ; Untyped              ;
; CBXI_PARAMETER                     ; altsyncram_ug81                ; Untyped              ;
+------------------------------------+--------------------------------+----------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Mon Mar 24 14:40:26 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sin_sample -c sin_sample
Info: Found 1 design units, including 1 entities, in source file sin_sample.bdf
    Info: Found entity 1: sin_sample
Info: Found 1 design units, including 1 entities, in source file address_gen.v
    Info: Found entity 1: address_gen
Info: Found 1 design units, including 1 entities, in source file ad_da.v
    Info: Found entity 1: ad_da
Info: Elaborating entity "sin_sample" for the top level hierarchy
Warning: Using design file trans_ad_da.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: trans_ad_da
Info: Elaborating entity "trans_ad_da" for hierarchy "trans_ad_da:inst3"
Warning (10230): Verilog HDL assignment warning at trans_ad_da.v(37): truncated value with size 32 to match size of target (14)
Warning: Using design file lpm_rom0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lpm_rom0
Info: Elaborating entity "lpm_rom0" for hierarchy "lpm_rom0:inst"
Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/71/quartus/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "lpm_rom0:inst|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "lpm_rom0:inst|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ug81.tdf
    Info: Found entity 1: altsyncram_ug81
Info: Elaborating entity "altsyncram_ug81" for hierarchy "lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated"
Info: Elaborating entity "address_gen" for hierarchy "address_gen:inst1"
Warning (10230): Verilog HDL assignment warning at address_gen.v(39): truncated value with size 32 to match size of target (5)
Info: Implemented 34 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 14 output pins
    Info: Implemented 5 logic cells
    Info: Implemented 14 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Allocated 139 megabytes of memory during processing
    Info: Processing ended: Mon Mar 24 14:40:30 2008
    Info: Elapsed time: 00:00:04