📄 8080 cpu .v
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end
end
`cpus_fetchi4: begin // complete instruction memory read
// We split off the instructions into 4 groups. Most of the 8080
// instructions are in the MOV and ACC operations class.
case (opcode[7:6]) // Decode top level
2'b00: begin // 00: Data transfers and others
case (opcode[5:0]) // decode these instructions
6'b000000: begin // NOP
// yes, do nothing
state <= `cpus_fetchi; // Fetch next instruction
pc <= pc+16'h1; // Next instruction byte
end
6'b110111: begin // STC
carry <= 1; // set carry flag
state <= `cpus_fetchi; // Fetch next instruction
pc <= pc+16'h1; // Next instruction byte
end
6'b111111: begin // CMC
carry <= ~carry; // complement carry flag
state <= `cpus_fetchi; // Fetch next instruction
pc <= pc+16'h1; // Next instruction byte
end
6'b101111: begin // CMA
regfil[`reg_a] <= ~regfil[`reg_a]; // complement accumulator
state <= `cpus_fetchi; // Fetch next instruction
pc <= pc+16'h1; // Next instruction byte
end
6'b100111: begin // DAA
// decimal adjust accumulator, or remove by carry any
// results in nybbles greater than 9
if (regfil[`reg_a][3:0] > 9 || auxcar)
{ auxcar, regfil[`reg_a] } <= regfil[`reg_a]+8'h06;
state <= `cpus_daa; // finish DAA
pc <= pc+16'h1; // Next instruction byte
end
6'b000100, 6'b001100, 6'b010100, 6'b011100, 6'b100100,
6'b101100, 6'b110100, 6'b111100, 6'b000101, 6'b001101,
6'b010101, 6'b011101, 6'b100101, 6'b101101, 6'b110101,
6'b111101: begin // INR/DCR
regd <= opcode[5:3]; // get source/destination reg
aluopra <= regfil[opcode[5:3]]; // load as alu a
aluoprb <= 1; // load 1 as alu b
if (opcode[0]) alusel <= `aluop_sub; // set subtract
else alusel <= `aluop_add; // set add
if (opcode[5:3] == `reg_m) begin
raddrhold <= regfil[`reg_h]<<8|regfil[`reg_l];
statesel <= `mac_indm; // inc/dec m
state <= `cpus_read; // read byte
end else state <= `cpus_indcb; // go inr/dcr cycleback
pc <= pc+16'h1; // Next instruction byte
end
6'b000010, 6'b010010: begin // STAX
wdatahold <= regfil[`reg_a]; // place A as source
if (opcode[4]) // use DE pair
waddrhold <= regfil[`reg_d]<<8|regfil[`reg_e];
else // use BC pair
waddrhold <= regfil[`reg_b] << 8|regfil[`reg_c];
statesel <= `mac_writebyte; // write byte
state <= `cpus_write;
pc <= pc+16'h1; // Next instruction byte
end
6'b001010, 6'b011010: begin // LDAX
regd <= `reg_a; // set A as destination
if (opcode[4]) // use DE pair
raddrhold <= regfil[`reg_d]<<8|regfil[`reg_e];
else // use BC pair
raddrhold <= regfil[`reg_b]<<8|regfil[`reg_c];
statesel <= `mac_readbtoreg; // read byte to register
state <= `cpus_read;
pc <= pc+16'h1; // Next instruction byte
end
6'b000111: begin // RLC
// rotate left circular
{ carry, regfil[`reg_a] } <=
(regfil[`reg_a] << 1)+regfil[`reg_a][7];
state <= `cpus_fetchi; // Fetch next instruction
pc <= pc+16'h1; // Next instruction byte
end
6'b010111: begin // RAL
// rotate left through carry
{ carry, regfil[`reg_a] } <= (regfil[`reg_a] << 1)+carry;
state <= `cpus_fetchi; // Fetch next instruction
pc <= pc+16'h1; // Next instruction byte
end
6'b001111: begin // RRC
// rotate right circular
regfil[`reg_a] <=
(regfil[`reg_a] >> 1)+(regfil[`reg_a][0] << 7);
carry <= regfil[`reg_a][0];
state <= `cpus_fetchi; // Fetch next instruction
pc <= pc+16'h1; // Next instruction byte
end
6'b011111: begin // RAR
// rotate right through carry
regfil[`reg_a] <= (regfil[`reg_a] >> 1)+(carry << 7);
carry <= regfil[`reg_a][0];
state <= `cpus_fetchi; // Fetch next instruction
pc <= pc+16'h1; // Next instruction byte
end
6'b001001: begin // DAD B
// add BC to HL
{ carry, regfil[`reg_h], regfil[`reg_l] } <=
(regfil[`reg_h] << 8)+regfil[`reg_l]+
(regfil[`reg_b] << 8)+regfil[`reg_c];
state <= `cpus_fetchi; // Fetch next instruction
pc <= pc+16'h1; // Next instruction byte
end
6'b011001: begin // DAD D
// add DE to HL
{ carry, regfil[`reg_h], regfil[`reg_l] } <=
(regfil[`reg_h] << 8)+regfil[`reg_l]+
(regfil[`reg_d] << 8)+regfil[`reg_e];
state <= `cpus_fetchi; // Fetch next instruction
pc <= pc+16'h1; // Next instruction byte
end
6'b101001: begin // DAD H
// add HL to HL
{ carry, regfil[`reg_h], regfil[`reg_l] } <=
(regfil[`reg_h] << 8)+regfil[`reg_l]+
(regfil[`reg_h] << 8)+regfil[`reg_l];
state <= `cpus_fetchi; // Fetch next instruction
pc <= pc+16'h1; // Next instruction byte
end
6'b111001: begin // DAD SP
// add SP to HL
{ carry, regfil[`reg_h], regfil[`reg_l] } <=
(regfil[`reg_h] << 8)+regfil[`reg_l]+sp;
state <= `cpus_fetchi; // Fetch next instruction
pc <= pc+16'h1; // Next instruction byte
end
6'b000011: begin // INX B
// increment BC, no flags set
regfil[`reg_b] <=
(((regfil[`reg_b] << 8)+regfil[`reg_c])+16'h1)>>8;
regfil[`reg_c] <=
((regfil[`reg_b] << 8)+regfil[`reg_c])+16'h1;
state <= `cpus_fetchi; // Fetch next instruction
pc <= pc+16'h1; // Next instruction byte
end
6'b010011: begin // INX D
// increment DE, no flags set
regfil[`reg_d] <=
(((regfil[`reg_d] << 8)+regfil[`reg_e])+16'h1)>>8;
regfil[`reg_e] <=
((regfil[`reg_d] << 8)+regfil[`reg_e])+16'h1;
state <= `cpus_fetchi; // Fetch next instruction
pc <= pc+16'h1; // Next instruction byte
end
6'b100011: begin // INX H
// increment HL, no flags set
regfil[`reg_h] <=
(((regfil[`reg_h] << 8)+regfil[`reg_l])+16'h1)>>8;
regfil[`reg_l] <=
((regfil[`reg_h] << 8)+regfil[`reg_l])+16'h1;
state <= `cpus_fetchi; // Fetch next instruction
pc <= pc+16'h1; // Next instruction byte
end
6'b110011: begin // INX SP
// increment SP, no flags set
sp <= sp + 16'b1;
state <= `cpus_fetchi; // Fetch next instruction
pc <= pc+16'h1; // Next instruction byte
end
6'b001011: begin // DCX B
// decrement BC, no flags set
regfil[`reg_b] <=
(((regfil[`reg_b] << 8)+regfil[`reg_c])-16'h1)>>8;
regfil[`reg_c] <=
((regfil[`reg_b] << 8)+regfil[`reg_c])-16'h1;
state <= `cpus_fetchi; // Fetch next instruction
pc <= pc+16'h1; // Next instruction byte
end
6'b011011: begin // DCX D
// decrement DE, no flags set
regfil[`reg_d] <=
(((regfil[`reg_d] << 8)+regfil[`reg_e])-16'h1)>>8;
regfil[`reg_e] <=
((regfil[`reg_d] << 8)+regfil[`reg_e])-16'h1;
state <= `cpus_fetchi; // Fetch next instruction
pc <= pc+16'h1; // Next instruction byte
end
6'b101011: begin // DCX H
// decrement HL, no flags set
regfil[`reg_h] <=
(((regfil[`reg_h] << 8)+regfil[`reg_l])-16'h1)>>8;
regfil[`reg_l] <=
((regfil[`reg_h] << 8)+regfil[`reg_l])-16'h1;
state <= `cpus_fetchi; // Fetch next instruction
pc <= pc+1'h1; // Next instruction byte
end
6'b111011: begin // DCX SP
// decrement SP, no flags set
sp <= sp-16'b1;
state <= `cpus_fetchi; // Fetch next instruction
pc <= pc+16'h1; // Next instruction byte
end
6'b000001: begin // LXI B
raddrhold <= pc+16'h1; // pick up after instruction
statesel <= `mac_readdtobc; // read double to BC
state <= `cpus_read;
pc <= pc+16'h3; // skip
end
6'b010001: begin // LXI D
raddrhold <= pc+16'h1; // pick up after instruction
statesel <= `mac_readdtode; // read double to DE
state <= `cpus_read;
pc <= pc+16'h3; // skip
end
6'b100001: begin // LXI H
raddrhold <= pc+16'h1; // pick up after instruction
statesel <= `mac_readdtohl; // read double to HL
state <= `cpus_read;
pc <= pc+16'h3; // skip
end
6'b110001: begin // LXI SP
raddrhold <= pc+16'h1; // pick up after instruction
statesel <= `mac_readdtosp; // read double to SP
state <= `cpus_read;
pc <= pc+16'h3; // skip
end
6'b000110, 6'b001110, 6'b010110, 6'b011110, 6'b100110,
6'b101110, 6'b110110, 6'b111110: begin // MVI
// move immediate to register
regd <= opcode[5:3]; // set destination register
raddrhold <= pc+16'h1; // set pickup address
if (opcode[5:3] == `reg_m) begin // it's mvi m,imm
regd <= opcode[5:3]; // set destination register
// set destination address
waddrhold <= { regfil[`reg_h], regfil[`reg_l] };
statesel <= `mac_readbmtw; // read byte and move to write
end else
statesel <= `mac_readbmtr; // read byte and move to register
state <= `cpus_read;
pc <= pc+16'h2; // advance over byte
end
6'b110010: begin // STA
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