📄 ide_control.v
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module ide_control(
clk_100M,reset_n,ready,current_state,
word_cnt,
dma_wden, dma_rden,
dma_datain, dma_dataout,
fifo_empty, dmatomem,
wd_clk, rd_clk,
dma_wren,
ide_dmarq,ide_dmack_n,
ide_datain,ide_dataout,
ide_diow_n,ide_dior_n,
ide_iordy,ide_intrq
);
input clk_100M,reset_n;
output ready;
reg ready;
input ide_dmarq,ide_intrq,ide_iordy;
output ide_diow_n,ide_dior_n,ide_dmack_n;
reg ide_diow_n,ide_dior_n,ide_dmack_n;
input[15:0] ide_datain;
output[15:0] ide_dataout;
reg[15:0] ide_dataout;
output dmatomem,dma_wren;
reg dmatomem,dma_wren;
input dma_wden,dma_rden,fifo_empty;
input[15:0] dma_datain;
output[15:0] dma_dataout;
reg[15:0] dma_dataout;
output rd_clk,wd_clk;
reg wd_clk;
output[8:0] word_cnt;
reg[8:0] word_cnt;
reg[7:0] sector_cnt;
reg clk_50M;
always@(posedge clk_100M)clk_50M<=~clk_50M;
reg pre_wden,pre_rden;
reg pos_wden,pos_rden;
always@(posedge clk_50M or negedge reset_n)begin
if(reset_n==1'b0)begin
pre_wden<=1'b0;
pre_rden<=1'b0;
pos_wden<=1'b0;
pos_rden<=1'b0;
end
else begin
pre_wden<=dma_wden;
pos_wden<=~pre_wden&dma_wden;
pre_rden<=dma_rden;
pos_rden<=~pre_rden&dma_rden;
end
end
reg pre_iordy,iordy_pos,iordy_neg;
always@(posedge clk_100M or negedge reset_n)begin
if(reset_n==1'b0)pre_iordy<=1'b0;
else begin
pre_iordy<=ide_iordy;
iordy_pos<=~pre_iordy&ide_iordy;
iordy_neg<=pre_iordy&~ide_iordy;
end
end
assign rd_clk=iordy_pos|iordy_neg;
output[29:0] current_state;
reg[29:0] current_state,next_state;
parameter IDLE = 30'b000000000000000000000000000001,
WRITE_WAIT_RQ_H = 30'b000000000000000000000000000010,
WRITE_DELAY1 = 30'b000000000000000000000000000100,
WRITE_CK_L = 30'b000000000000000000000000001000,
WRITE_DELAY2 = 30'b000000000000000000000000010000,
WRITE_DIOW_L = 30'b000000000000000000000000100000,
WRITE_DELAY3 = 30'b000000000000000000000001000000,
WRITE_WAIT_IO_L = 30'b000000000000000000000010000000,
WRITE_SETDATA = 30'b000000000000000000000100000000,
WRITE_SETDIOR = 30'b000000000000000000001000000000,
WRITE_DELAY4 = 30'b000000000000000000010000000000,
WRITE_DIOW_H = 30'b000000000000000000100000000000,
WRITE_DELAY5 = 30'b000000000000000001000000000000,
CRC_SETDATA = 30'b000000000000000010000000000000,
CRC_DELAY1 = 30'b000000000000000100000000000000,
CRC_CK_H = 30'b000000000000001000000000000000,
CRC_DELAY2 = 30'b000000000000010000000000000000,
CRC_END = 30'b000000000000100000000000000000;
/*
READ_RQ_H = 30'b000000000000000010000000000000,
READ_DELAY1 = 30'b000000000000000100000000000000,
READ_CK_L = 30'b000000000000001000000000000000,
READ_DELAY2 = 30'b000000000000010000000000000000,
READ_DIOx_L = 30'b000000000000100000000000000000,
READ_DATA = 30'b000000000001000000000000000000,
READ_DELAY3 = 30'b000000000010000000000000000000,
READ_WAIT_RQ_L = 30'b000000000100000000000000000000,
READ_DELAY4 = 30'b000000001000000000000000000000,
READ_DIOx_H = 30'b000000010000000000000000000000,
READ_DELAY5 = 30'b000000100000000000000000000000,
*/
reg[7:0] delay_cnt;
always@(posedge clk_100M or negedge reset_n)
if(!reset_n)current_state<=IDLE;
else current_state<=next_state;
always@(current_state)begin
//next_state=IDLE;
case(current_state)
IDLE :
if(pos_wden==1'b1)next_state=WRITE_WAIT_RQ_H;
//else if(rden==1)next_state=READ_RQ_H;
else next_state=IDLE;
WRITE_WAIT_RQ_H :
if(ide_dmarq==1'b1)next_state=WRITE_DELAY1;
else next_state=WRITE_WAIT_RQ_H;
WRITE_DELAY1 :
if(delay_cnt==8'd100)next_state=WRITE_CK_L;
else next_state=WRITE_DELAY1;
WRITE_CK_L : next_state=WRITE_DELAY2;
WRITE_DELAY2 :
if(delay_cnt==8'd4)next_state=WRITE_DIOW_L;
else next_state=WRITE_DELAY2;
WRITE_DIOW_L : next_state=WRITE_DELAY3;
WRITE_DELAY3 :
if(delay_cnt==8'd4)next_state=WRITE_WAIT_IO_L;
else next_state=WRITE_DELAY3;
WRITE_WAIT_IO_L :
if(ide_iordy==1'b0)next_state=WRITE_SETDATA;
else next_state=WRITE_WAIT_IO_L;
WRITE_SETDATA :
if(ide_dmarq==1'b0)next_state=WRITE_DIOW_H;
else if(word_cnt[8])next_state=WRITE_SETDATA;
else next_state=WRITE_SETDIOR;
WRITE_SETDIOR : begin
if(ide_iordy==1'd0)next_state=WRITE_DELAY4;
else next_state=WRITE_SETDIOR;
end
WRITE_DELAY4 : begin
if(delay_cnt==8'd2)next_state=WRITE_SETDATA;
else next_state=WRITE_DELAY4;
end
WRITE_DIOW_H : next_state=WRITE_DELAY5;
WRITE_DELAY5 : begin
if(delay_cnt>=8'd10)next_state=CRC_SETDATA;
else next_state=WRITE_DELAY5;
end
CRC_SETDATA : next_state=CRC_DELAY1;
CRC_DELAY1 :
if(delay_cnt>=8'd12)next_state=CRC_CK_H;
else next_state=CRC_DELAY1;
CRC_CK_H : next_state=CRC_DELAY2;
CRC_DELAY2 :
if(delay_cnt>=8'd15)next_state=CRC_END;
else next_state=CRC_DELAY2;
CRC_END : next_state=IDLE;
//default : next_state=IDLE;
endcase
end
always@(posedge clk_100M or negedge reset_n)
if(!reset_n)begin
ide_dmack_n<=1; ide_diow_n<=1; ide_dior_n <=1;
ready<=0; word_cnt<=9'd0;
dmatomem<=1'b0; sector_cnt<=8'd0;
dma_wren<=1'b0;
end
else case(next_state)
//----------------------------------------------------------------
IDLE: begin
ready<=1'b1;
word_cnt<=9'd0;
ide_dmack_n<=1'b1;
ide_diow_n<=1'b1;
ide_dior_n<=1'b1;
dma_wren<=1'b0;
dmatomem <=1'b0;
crcout<=16'h4aba;
delay_cnt<=8'd0;
end
WRITE_WAIT_RQ_H : begin
ready<=1'b0;
dma_wren<=1'b1;
word_cnt<=9'h000;
end
WRITE_DELAY1 : delay_cnt <= delay_cnt+1'b1;
WRITE_CK_L : begin
delay_cnt<=8'd0;
ide_dmack_n<=0;
end
WRITE_DELAY2 : delay_cnt <= delay_cnt+1'b1;
WRITE_DIOW_L : begin
delay_cnt<=8'd0; ide_diow_n<=0;
end
WRITE_DELAY3 : delay_cnt <= delay_cnt+1'b1;
// WRITE_WAIT_IO_L : begin
// end
WRITE_SETDATA : begin
//delay_cnt <= delay_cnt+1'b1;
ide_dataout<={7'b0,word_cnt};
end
WRITE_SETDIOR : begin
if(ide_iordy==1'b0)begin
ide_dior_n <= ~ide_dior_n;//wd_clk;
word_cnt <= word_cnt+1'b1;
crcout <= crcin;
delay_cnt <= 8'd0;
end
end
WRITE_DELAY4 : delay_cnt <= delay_cnt+1'b1;
WRITE_DIOW_H : begin
delay_cnt<=8'd0; ide_diow_n<=1'b1;
end
WRITE_DELAY5 : delay_cnt <= delay_cnt+1'b1;
//--------------------------------------------------------------------------
CRC_SETDATA : begin
delay_cnt<=8'd0; dma_wren<=1'b1;
ide_dataout<=crcout;
end
CRC_DELAY1 : delay_cnt <= delay_cnt+1'b1;
CRC_CK_H : begin
delay_cnt<=8'd0; ide_dmack_n<=1'b1;
end
CRC_DELAY2 : delay_cnt <= delay_cnt+1'b1;
CRC_END : begin
delay_cnt<=8'd0;
end
endcase
reg[15:0] crcout;
wire[16:1] f;
wire[15:0] crcin,din;
assign din=(dma_wren)?ide_dataout:16'h0000;//ide_datain;
assign crcin[0] =f[16];
assign crcin[1] =f[15];
assign crcin[2] =f[14];
assign crcin[3] =f[13];
assign crcin[4] =f[12];
assign crcin[5] =f[11] ^ f[16];
assign crcin[6] =f[10] ^ f[15];
assign crcin[7] =f[9] ^f[14];
assign crcin[8] =f[8] ^f[13];
assign crcin[9] =f[7] ^f[12];
assign crcin[10] =f[6] ^f[11];
assign crcin[11] =f[5] ^f[10];
assign crcin[12] =f[4] ^f[9] ^f[16];
assign crcin[13] =f[3] ^f[8] ^f[15];
assign crcin[14] =f[2] ^f[7] ^f[14];
assign crcin[15] =f[1] ^f[6] ^f[13];
assign f[1] =din[0] ^ crcout[15];
assign f[2] =din[1] ^ crcout[14];
assign f[3] =din[2] ^ crcout[13];
assign f[4] =din[3] ^ crcout[12];
assign f[5] =din[4] ^ crcout[11] ^f[1];
assign f[6] =din[5] ^ crcout[10] ^f[2];
assign f[7] =din[6] ^ crcout[9] ^f[3];
assign f[8] =din[7] ^ crcout[8] ^f[4];
assign f[9] =din[8] ^ crcout[7] ^f[5];
assign f[10] =din[9] ^ crcout[6] ^f[6];
assign f[11] =din[10] ^ crcout[5] ^f[7];
assign f[12] =din[11] ^ crcout[4] ^f[1] ^f[8];
assign f[13] =din[12] ^ crcout[3] ^f[2] ^f[9];
assign f[14] =din[13] ^ crcout[2] ^f[3] ^f[10];
assign f[15] =din[14] ^ crcout[1] ^f[4] ^f[11];
assign f[16] =din[15] ^ crcout[0] ^f[5] ^f[12];
endmodule
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