count_plus_last.txt

来自「对电机的编码器输入的正交编码信号进行4倍频处理」· 文本 代码 · 共 248 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;	
entity zibm is
    port(
	     clk,plusa,plusb,reset: in std_logic;
		  plus_out,dir_out :out  std_logic;
		  ---------------------------------------------
		   plus_cnt :out integer range 0 to 255
	 );

end zibm;
architecture Behavioral of zibm is
signal plus_out1,plus_out2 : std_logic;
signal plus1 : std_logic;
signal plus1_low_ensure1 ,plus1_low_ensure2: std_logic;
signal  plusa_low_ensure: std_logic;
----------------------------------------jiashanqu-----------------
signal  plus_buff,plus_buff_check,dir_out_buff: std_logic;
---------------------------------------------------------------
signal plus_chu1,plus_chu2,plus_chu_buff1,plus_chu_buff2 :std_logic;
begin
 plus1<=plusa  xor  plusb;
------------------------------------------plus1上升------------------

process(clk,reset,plus1,plus_out1,plus1_low_ensure1)
variable plus_kuan1 : integer;
begin
if(reset='0') then
	  plus_out1<='0';	
	  plus1_low_ensure1<='0';
	  plus_kuan1:=0;
	   plus_chu1<='0';
else
----------------------
   if( plus_out1='1')then
	    if(plus_kuan1<1) then
	        if(clk'event and clk='1')  then        
	                       
					   plus_chu1<=plus_chu_buff1;
						plus_kuan1:=plus_kuan1+1;
			  end if;
			else
			 plus_kuan1:=0;
			 plus_chu1<='0';
			 plus_out1<='1';
			 end if; 
				  
--------------------------------------
   else
	 if(plus1_low_ensure1='0') then
	 
	  if(clk'event and clk='1')  then
         if(plus1='0') then		
			
					 plus1_low_ensure1<='1';		 
				
			else
			  plus1_low_ensure1<='0';
		    	plus_out1<='0';	
				
			end if;
		end if;
	else	
		
		if(clk'event and clk='1')  then
              if(plus1='1') then
			         plus_chu_buff1<='1';
					     plus_out1<='1';
						 
						   plus1_low_ensure1<='0';
					
				else  
			   	plus_chu_buff1<='0';
			    	plus1_low_ensure1<='1';
	         end if;
     end if;
 end if;
end if;
	 end if;    
end process;

---------------------------------------------------plus1下降--------------------
process(clk,reset,plus1,plus_out2,plus1_low_ensure2)
 variable plus_kuan2: integer;
begin
if(reset='0') then
	  plus_out2<='0';	
	  plus1_low_ensure2<='0';
	  	  plus_kuan2:=0;
	   plus_chu2<='0';
else
      if( plus_out2='1')then
		     if(plus_kuan2<1) then
	            if(clk'event and clk='1')  then
              
					   plus_chu2<=plus_chu_buff2;
						plus_kuan2:=plus_kuan2+1;
						end if;
						
			 else
			 plus_out2<='1';
			 plus_kuan2:=0;
			 plus_chu2<='0';
			 end if;
	else 
		if(plus1_low_ensure2='0') then
	 
   	  if(clk'event and clk='1')  then
         if(plus1='1') then		
			
					 plus1_low_ensure2<='1';		 
				
			else
			  plus1_low_ensure2<='0';
		    	plus_out2<='0';	
				
			end if;
		end if;
	else	
		
		if(clk'event and clk='1')  then
              if(plus1='0') then
			         
					     plus_out2<='1';
						 plus_chu_buff2<='1';
						   plus1_low_ensure2<='0';
					
				else  
				plus_chu_buff2<='0';
			    	plus1_low_ensure2<='1';
	         end if;
     end if;
 end if;
end if;
	 end if;   
end process;

------------------------------------各路输出组合-------------------------
--	plus_out<=plus_out1	or 	plus_out2;	
  plus_buff<=plus_chu1	or 	plus_chu2;	
 
 process(clk,reset,plus_buff)
  begin
  if(reset='0' ) then
     plus_out<= '0';
else
  if(clk'event and clk='1' ) then
    plus_out<=plus_buff;
  end if;	 
  end if;
 end process;

---------------------------------------------方向确定-------------------------
process(clk,reset,plusa_low_ensure)

begin
if(reset='0') then
     dir_out <='0';
	  dir_out_buff<='0';
	   plusa_low_ensure <='0'	;
	--	plusa_low2_ensure <='0'	;
else
-----------------------------------
if(plusa_low_ensure ='0') then
    if(clk'event and clk='1')  then
        if(plusb='0') then
      
		            if(plusa='0')  then
						         plusa_low_ensure <='1' ;
						else 
                           plusa_low_ensure <='0'	;
                  end if;	
         else 
	         plusa_low_ensure <='0'	;		
         							
			  end if;	
   	  
	 end if;					
 else
   if(clk'event and clk='1')  then
            if(plusa='1')  then
						dir_out<='1';
						  dir_out_buff<='1';
						plusa_low_ensure <='0' ;  
				else
				      if(plusb='1') then
                  	plusa_low_ensure <='0' ; 			
                    dir_out<='0';
						    dir_out_buff<='0';
						  else
						  plusa_low_ensure <='1' ;  
						  end if;
             end if;	
      end if;	

 end if;  
-------------------------------------------------------------------------
----------------------------------------------------------  
end if;    
 end process; 	
 
------------------------------------count plus_buff----------------------
 process(clk,reset,plus_buff,plus_buff_check)
 variable cnt :integer range 0 to 255;
begin
    if(reset='0') then
	 cnt:=0;
	 plus_cnt<=0;
	 plus_buff_check<='0';

 else
	 if(plus_buff_check='0') then
	     if(clk'event and clk='1') then
		       if(plus_buff='0') then
				     plus_buff_check<='1';
				  else
        				 plus_buff_check<='0';  
					end if;	 
		  end if;
	else
   if(clk'event and clk='1') then	
		   if(plus_buff='1') then
			     if(  dir_out_buff='1') then
                      if(cnt=255) then
				              cnt:=0;
				            else
                        cnt:= cnt+1;				  
					        end if;
              else
                   if(cnt=0) then
                        cnt:=255;
                    else
                         cnt:=cnt-1;
                    end if;	
					end if;	 
          else
            plus_buff_check<='0';   	
         end if;  				
    end if;		
  end if;	
  plus_cnt<=cnt;
end if;	  
end process;
 
 
end architecture;