tb_hwtb_ddr1_top.vhd

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-------------------------------------------------------------------------------
-- Copyright (c) 2006 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor: Xilinx
-- \   \   \/    Version: 1.1
--  \   \        Filename: tb_HWTB_ddr1_top.vhd
--  /   /        Date Last Modified: 5/11/06
-- /___/   /\    Date Created:
-- \   \  /  \
--  \___\/\___\
-- 
--Device: Virtex-5
--Purpose: Clock generation logic. Instantiates DCM and global clock
--         buffers for CLK0, CLK90. Instantiates IDELAYCTRL (only one IDELAY
--         instantiated - MAP should replicate these as appropriate for user 
--         design; user can also add more IDELAYCTRLs explicitly as required)
--Reference:
--    XAPP851
--Revision History:
--    Rev 1.0 - Internal release. Author: Toshihiko Moriyama. 4/29/06.
--    Rev 1.1 - External release. Added header. Changed CK/CK_n to vector.
--              5/11/06.
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library work;
use work.ddr1_parameters.all;

entity tb_hwtb_ddr1_top is
end tb_hwtb_ddr1_top;

architecture sim of tb_hwtb_ddr1_top is

	-- verilog DDR1 SDRAM memory module from Micron
	COMPONENT ddr IS
    PORT (
        Dq    : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => 'Z');
        Dqs   : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
        Addr  : IN    STD_LOGIC_VECTOR (12 DOWNTO 0);
        Ba    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0);
        Clk   : IN    STD_LOGIC;
        Clk_n : IN    STD_LOGIC;
        Cke   : IN    STD_LOGIC;
        Cs_n  : IN    STD_LOGIC;
        Ras_n : IN    STD_LOGIC;
        Cas_n : IN    STD_LOGIC;
        We_n  : IN    STD_LOGIC;
        Dm    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0)
    );
	END COMPONENT;

	component hwtb_ddr1_top is
	port (
	rst_n			: in	std_logic;
	clk_in_p		: in	std_logic;
	clk_in_n		: in	std_logic;
	clk200_in_p		: in	std_logic;
	clk200_in_n		: in	std_logic;

	CKE			: out	std_logic;
	CK_p			: out	std_logic_vector(clk_width - 1 downto 0);
	CK_n			: out	std_logic_vector(clk_width - 1 downto 0);
	AD			: out	std_logic_vector(row_address - 1 downto 0);
	BA			: out	std_logic_vector(bank_address - 1 downto 0);
	CS_n			: out	std_logic_vector(no_of_cs - 1 downto 0);
	RAS_n			: out	std_logic;
	CAS_n			: out	std_logic;
	WE_n			: out	std_logic;
	DM				: out	std_logic_vector(dm_per_comp * no_of_comps - 1 downto 0);
	DQ				: inout	std_logic_vector(dq_per_comp * no_of_comps - 1 downto 0);
	DQS				: inout	std_logic_vector(dqs_per_comp * no_of_comps - 1 downto 0);

	phy_error		: out	std_logic;
	error			: out	std_logic;
	dcm_locked		: out	std_logic;
	ctrl_ready		: out	std_logic

	);
	end component;

	signal clk_in			: std_logic;
	signal clk200_in		: std_logic;
	signal clk_in_p			: std_logic;
	signal clk_in_n			: std_logic;
	signal clk200_in_p		: std_logic;
	signal clk200_in_n		: std_logic;
	signal rst_n			: std_logic;

	signal CKE				: std_logic;
	signal CK				: std_logic_vector(clk_width - 1 downto 0);
	signal CK_n				: std_logic_vector(clk_width - 1 downto 0);
	signal AD				: std_logic_vector(row_address - 1 downto 0);
	signal BA				: std_logic_vector(bank_address - 1 downto 0);
	signal CS_n				: std_logic_vector(no_of_cs - 1 downto 0);
	signal RAS_n			: std_logic;
	signal CAS_n			: std_logic;
	signal WE_n				: std_logic;
	signal DM				: std_logic_vector(dm_per_comp * no_of_comps - 1 downto 0);
	signal DQ				: std_logic_vector(dq_per_comp * no_of_comps - 1 downto 0);
	signal DQS				: std_logic_vector(dqs_per_comp * no_of_comps - 1 downto 0);

	signal phy_error		: std_logic;
	signal error			: std_logic;
	signal dcm_locked		: std_logic;
	signal ctrl_ready		: std_logic;

	constant CLK_PERIOD		: TIME := 5 ns;
	constant CLK200_PERIOD	: TIME := 5 ns;

begin

	P_CLK : process begin
		clk_in	<=	'1';	wait for CLK_PERIOD/2 ;
		clk_in	<=	'0';	wait for CLK_PERIOD/2 ;
	end process ;

	clk_in_p <= clk_in;
	clk_in_n <= not clk_in;

	P_CLK200 : process begin
		clk200_in	<=	'1';	wait for CLK200_PERIOD/2 ;
		clk200_in	<=	'0';	wait for CLK200_PERIOD/2 ;
	end process ;

	clk200_in_p <= clk200_in;
	clk200_in_n <= not clk200_in;

	P_RST : process begin
		rst_n <= '0';
		rst_n <= '1';
		wait;
	end process ;


	HWTB_DDR1_TOP_I : hwtb_ddr1_top
	port map (
	rst_n			=> rst_n,
	clk_in_p		=> clk_in_p,
	clk_in_n		=> clk_in_n,

	clk200_in_p		=> clk200_in_p,
	clk200_in_n		=> clk200_in_n,

	CKE				=> CKE,
	CK_p			=> CK,
	CK_n			=> CK_n,
	AD				=> AD,
	BA				=> BA,
	CS_n			=> CS_n,
	RAS_n			=> RAS_n,
	CAS_n			=> CAS_n,
	WE_n			=> WE_n,
	DM				=> DM,
	DQ				=> DQ,
	DQS				=> DQS,

	phy_error		=> phy_error,
	error			=> error,
	dcm_locked		=> dcm_locked,
	ctrl_ready		=> ctrl_ready
	);

	G_DDR1 : for I in 0 to no_of_comps-1  generate

	DDR1_MEMORY : ddr
        PORT MAP (
        Dq	=> DQ(dq_per_comp*(I+1) - 1 downto dq_per_comp*I),
        Dqs	=> DQS(dqs_per_comp*(I+1) - 1 downto dqs_per_comp*I),
        Addr	=> AD,
        Ba	=> BA,
        Clk	=> CK(I),
        Clk_n	=> CK_n(I),
        Cke	=> CKE,
        Cs_n	=> CS_n(0),
        Ras_n	=> RAS_n,
        Cas_n	=> CAS_n,
        We_n	=> WE_n,
        Dm	=> DM(dm_per_comp*(I+1) - 1 downto dm_per_comp*I)
        );

	end generate;


end sim;