hwtb_ddr1_top.ucf

The xapp851.zip archive includes the following subdirectories. The specific contents of each subdi

NET "DQ<*>"             IOSTANDARD = SSTL2_II;
NET "DQS<*>"            IOSTANDARD = SSTL2_II;
NET "AD<*>"             IOSTANDARD = SSTL2_II;
NET "BA<*>"             IOSTANDARD = SSTL2_II;
NET "CKE"               IOSTANDARD = SSTL2_II;
NET "CS_n<*>"           IOSTANDARD = SSTL2_II;
NET "RAS_n"             IOSTANDARD = SSTL2_II;
NET "CAS_n"             IOSTANDARD = SSTL2_II;
NET "WE_n"              IOSTANDARD = SSTL2_II;
NET "DM<*>"             IOSTANDARD = SSTL2_II;
NET "CK_p<*>"           IOSTANDARD = DIFF_SSTL2_II;
NET "CK_n<*>"           IOSTANDARD = DIFF_SSTL2_II;

NET "clk_in_p"          IOSTANDARD = LVDS_25;
NET "clk_in_n"          IOSTANDARD = LVDS_25;
NET "clk200_in_p"       IOSTANDARD = LVDS_25;
NET "clk200_in_n"       IOSTANDARD = LVDS_25;
NET "error"             IOSTANDARD = LVCMOS25;
NET "phy_error"         IOSTANDARD = LVCMOS25;
NET "dcm_locked"        IOSTANDARD = LVCMOS25;
NET "rst_n"             IOSTANDARD = LVCMOS25;
NET "ctrl_ready"        IOSTANDARD = LVCMOS25;

###############################################################################
# Lock slice flops for second/third rank of flip-flops for read data 
# synchronization from DQS->FPGA clock domain
# NOTES:
#  1. We're concerned mainly with the skew between first bit of each DQS strobe
#     group (which is used for calibration) and all other bits in that group 
#     (which aren't used for calibration). Indirectly control skew by putting
#     MAXDELAY contraint on path between first (DQS clock domain) and second 
#     (FPGA clock domain) rank of flip-flops.
#  2. For future design, integrate the second/third rank of flip-flops in the 
#     read capture path into the ISERDES. This requires other changes in the 
#     code to support DQS->FPGA clock capture on rising edge of FPGA clock only
#     (current scheme allows clock capture on either edge (determined during 
#     calibration) of FPGA clock. Using the ISERDES flops saves a ton of hassle
#     during implementation as far as having to specify location of slice flip-
#     flops (want to play close to respective IOB), as well as MAXDELAY 
#     constraints (to reduce skew - meeting this MAXDELAY constraint in fact 
#     becomes the critical path in meeting timing)
###############################################################################

NET "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/DQ_iddr_r[*]" MAXDELAY = 575ps;
NET "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/DQ_iddr_f[*]" MAXDELAY = 575ps;
NET "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/DQ_iddr_r[*]" MAXDELAY = 575ps;
NET "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/DQ_iddr_f[*]" MAXDELAY = 575ps;

########################################

INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.0.FD_DQ_IDDR_R180"     LOC=SLICE_X1Y40;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.0.FD_DQ_IDDR_R0"       LOC=SLICE_X0Y40;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.1.FD_DQ_IDDR_R180"     LOC=SLICE_X1Y40;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.1.FD_DQ_IDDR_R0"       LOC=SLICE_X0Y40;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.2.FD_DQ_IDDR_R180"     LOC=SLICE_X1Y41;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.2.FD_DQ_IDDR_R0"       LOC=SLICE_X0Y41;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.3.FD_DQ_IDDR_R180"     LOC=SLICE_X1Y41;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.3.FD_DQ_IDDR_R0"       LOC=SLICE_X0Y41;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.4.FD_DQ_IDDR_R180"     LOC=SLICE_X1Y42;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.4.FD_DQ_IDDR_R0"       LOC=SLICE_X0Y42;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.5.FD_DQ_IDDR_R180"     LOC=SLICE_X1Y42;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.5.FD_DQ_IDDR_R0"       LOC=SLICE_X0Y42;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.6.FD_DQ_IDDR_R180"     LOC=SLICE_X1Y43;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.6.FD_DQ_IDDR_R0"       LOC=SLICE_X0Y43;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.7.FD_DQ_IDDR_R180"     LOC=SLICE_X1Y43;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.7.FD_DQ_IDDR_R0"       LOC=SLICE_X0Y43;

########################################

INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.0.FD_DQ_IDDR_R180"     LOC=SLICE_X1Y56;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.0.FD_DQ_IDDR_R0"       LOC=SLICE_X0Y56;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.1.FD_DQ_IDDR_R180"     LOC=SLICE_X1Y56;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.1.FD_DQ_IDDR_R0"       LOC=SLICE_X0Y56;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.2.FD_DQ_IDDR_R180"     LOC=SLICE_X1Y57;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.2.FD_DQ_IDDR_R0"       LOC=SLICE_X0Y57;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.3.FD_DQ_IDDR_R180"     LOC=SLICE_X1Y57;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.3.FD_DQ_IDDR_R0"       LOC=SLICE_X0Y57;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.4.FD_DQ_IDDR_R180"     LOC=SLICE_X1Y58;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.4.FD_DQ_IDDR_R0"       LOC=SLICE_X0Y58;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.5.FD_DQ_IDDR_R180"     LOC=SLICE_X1Y58;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.5.FD_DQ_IDDR_R0"       LOC=SLICE_X0Y58;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.6.FD_DQ_IDDR_R180"     LOC=SLICE_X1Y59;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.6.FD_DQ_IDDR_R0"       LOC=SLICE_X0Y59;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.7.FD_DQ_IDDR_R180"     LOC=SLICE_X1Y59;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.7.FD_DQ_IDDR_R0"       LOC=SLICE_X0Y59;

########################################
# Falling Edge
########################################

INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.0.FD_DQ_IDDR_F180"     LOC=SLICE_X0Y40;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.0.FD_DQ_IDDR_F0"       LOC=SLICE_X1Y40;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.1.FD_DQ_IDDR_F180"     LOC=SLICE_X0Y40;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.1.FD_DQ_IDDR_F0"       LOC=SLICE_X1Y40;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.2.FD_DQ_IDDR_F180"     LOC=SLICE_X0Y41;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.2.FD_DQ_IDDR_F0"       LOC=SLICE_X1Y41;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.3.FD_DQ_IDDR_F180"     LOC=SLICE_X0Y41;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.3.FD_DQ_IDDR_F0"       LOC=SLICE_X1Y41;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.4.FD_DQ_IDDR_F180"     LOC=SLICE_X0Y42;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.4.FD_DQ_IDDR_F0"       LOC=SLICE_X1Y42;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.5.FD_DQ_IDDR_F180"     LOC=SLICE_X0Y42;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.5.FD_DQ_IDDR_F0"       LOC=SLICE_X1Y42;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.6.FD_DQ_IDDR_F180"     LOC=SLICE_X0Y43;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.6.FD_DQ_IDDR_F0"       LOC=SLICE_X1Y43;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.7.FD_DQ_IDDR_F180"     LOC=SLICE_X0Y43;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.0.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.7.FD_DQ_IDDR_F0"       LOC=SLICE_X1Y43;

########################################

INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.0.FD_DQ_IDDR_F180"     LOC=SLICE_X0Y56;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.0.FD_DQ_IDDR_F0"       LOC=SLICE_X1Y56;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.1.FD_DQ_IDDR_F180"     LOC=SLICE_X0Y56;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.1.FD_DQ_IDDR_F0"       LOC=SLICE_X1Y56;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.2.FD_DQ_IDDR_F180"     LOC=SLICE_X0Y57;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.2.FD_DQ_IDDR_F0"       LOC=SLICE_X1Y57;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.3.FD_DQ_IDDR_F180"     LOC=SLICE_X0Y57;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.3.FD_DQ_IDDR_F0"       LOC=SLICE_X1Y57;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.4.FD_DQ_IDDR_F180"     LOC=SLICE_X0Y58;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.4.FD_DQ_IDDR_F0"       LOC=SLICE_X1Y58;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.5.FD_DQ_IDDR_F180"     LOC=SLICE_X0Y58;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.5.FD_DQ_IDDR_F0"       LOC=SLICE_X1Y58;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.6.FD_DQ_IDDR_F180"     LOC=SLICE_X0Y59;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.6.FD_DQ_IDDR_F0"       LOC=SLICE_X1Y59;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.7.FD_DQ_IDDR_F180"     LOC=SLICE_X0Y59;
INST "DDR1_TOP_I/PHY_TOP_I/G_RD.1.PHY_DATA_READ_I/PHY_DQ_ALIGN_I/G_RD_FF.7.FD_DQ_IDDR_F0"       LOC=SLICE_X1Y59;

###############################################################################
# Uncomment if need to hardcode IDELAYCTRL (tool should do this automatically
# for us)
###############################################################################

## INST "CLK_MODULE_I/DLYCTRL0" LOC = "IDELAYCTRL_X0Y2";