hwtb_ddr1_top.ucf

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###############################################################################
## Copyright (c) 2006 Xilinx, Inc.
## This design is confidential and proprietary of Xilinx, All Rights Reserved.
###############################################################################
##   ____  ____
##  /   /\/   /
## /___/  \  /   Vendor: Xilinx
## \   \   \/    Version: 1.0
##  \   \        Filename: hwtb_ddr1_top.prj
##  /   /        Date Last Modified: 5/10/06
## /___/   /\    Date Created:
## \   \  /  \
##  \___\/\___\
## 
##Device: Virtex-5
##Purpose: Sample ISE constraint file. Pin and slice location 
##         constraints are based on the ML561 evaluation board using a 
##         5VLX50T-FF1136 part.
##Reference:
##    XAPP851
##Revision History:
##    Rev 1.0 - Internal release. Author: Toshihiko Moriyama. 4/29/06.
##    Rev 1.1 - External release. Added header. Changed hierarchical paths to 
##              support Synplify. Removed and reorganized various commented 
##              constraints. Added various timing comments. Added IOSTANDARD
##              for "N" terminal of each diff pair (not necessary, but just 
##              for completeness). Increase MAXDELAY constraint slightly.
##              5/10/06.
###############################################################################

###############################################################################
# Clock period constraints. Slight overconstrain on clock frequency because 
# we can get away with it (on V5 design)
###############################################################################

NET "clk_in" TNM_NET = "clk_in";
TIMESPEC "TS_clk_in" = PERIOD "clk_in" 4.5 ns HIGH 50 %;
NET "DQS<0>" TNM_NET = FFS(*) "DQS_0";
TIMESPEC "TS_DQS_0" = PERIOD "DQS_0" 4.5 ns HIGH 50 %;
NET "DQS<1>" TNM_NET = FFS(*) "DQS_1";
TIMESPEC "TS_DQS_1" = PERIOD "DQS_1" 4.5 ns HIGH 50 %;

###############################################################################
# Pinout (based on ML561 Evaluation Board)
###############################################################################

NET "AD<0>"             LOC = "M32";             # DDR1_A0
NET "AD<1>"             LOC = "L33";             # DDR1_A1
NET "AD<2>"             LOC = "K32";             # DDR1_A2
NET "AD<3>"             LOC = "K34";             # DDR1_A3
NET "AD<4>"             LOC = "L34";             # DDR1_A4
NET "AD<5>"             LOC = "J34";             # DDR1_A5
NET "AD<6>"             LOC = "H34";             # DDR1_A6
NET "AD<7>"             LOC = "H33";             # DDR1_A7
NET "AD<8>"             LOC = "F34";             # DDR1_A8
NET "AD<9>"             LOC = "G33";             # DDR1_A9
NET "AD<10>"            LOC = "E33";             # DDR1_A10
NET "AD<11>"            LOC = "E32";             # DDR1_A11
NET "AD<12>"            LOC = "E34";             # DDR1_A12
NET "BA<0>"             LOC = "AK33";            # DDR1_BA0
NET "BA<1>"             LOC = "AK34";            # DDR1_BA1
NET "CS_n<0>"           LOC = "AB33";            # DDR1_BY0_1_CS_N
NET "CAS_n"             LOC = "AC32";            # DDR1_CAS_N
NET "RAS_n"             LOC = "AB32";            # DDR1_RAS_N
NET "WE_n"              LOC = "AD34";            # DDR1_WE_N
NET "CK_n<0>"           LOC = "AJ34";            # DDR1_CK1_N
NET "CK_p<0>"           LOC = "AH34";            # DDR1_CK1_P
NET "CKE"               LOC = "AC34";            # DDR1_CKE
NET "DM<0>"             LOC = "AG32";            # DDR1_DM_BY0
NET "DM<1>"             LOC = "Y32";             # DDR1_DM_BY1
NET "DQS<0>"            LOC = "AD32";            # DDR1_DQS_BY0_P
NET "DQS<1>"            LOC = "AF33";            # DDR1_DQS_BY1_P
NET "DQ<0>"             LOC = "AP32";            # DDR1_DQ_BY0_B0
NET "DQ<1>"             LOC = "AN32";            # DDR1_DQ_BY0_B1
NET "DQ<2>"             LOC = "AN33";            # DDR1_DQ_BY0_B2
NET "DQ<3>"             LOC = "AN34";            # DDR1_DQ_BY0_B3
NET "DQ<4>"             LOC = "AM32";            # DDR1_DQ_BY0_B4
NET "DQ<5>"             LOC = "AM33";            # DDR1_DQ_BY0_B5
NET "DQ<6>"             LOC = "AL33";            # DDR1_DQ_BY0_B6
NET "DQ<7>"             LOC = "AL34";            # DDR1_DQ_BY0_B7
NET "DQ<8>"             LOC = "Y34";             # DDR1_DQ_BY1_B0
NET "DQ<9>"             LOC = "AA34";            # DDR1_DQ_BY1_B1
NET "DQ<10>"            LOC = "AA33";            # DDR1_DQ_BY1_B2
NET "DQ<11>"            LOC = "Y33";             # DDR1_DQ_BY1_B3
NET "DQ<12>"            LOC = "V34";             # DDR1_DQ_BY1_B4
NET "DQ<13>"            LOC = "W34";             # DDR1_DQ_BY1_B5
NET "DQ<14>"            LOC = "V33";             # DDR1_DQ_BY1_B6
NET "DQ<15>"            LOC = "V32";             # DDR1_DQ_BY1_B7

NET "clk200_in_n"       LOC = "AH22";            # DIRECT_CLK_TO_FPGA1_N
NET "clk200_in_p"       LOC = "AG22";            # DIRECT_CLK_TO_FPGA1_P
NET "clk_in_n"          LOC = "AG13" ;           # EXT_CLK_TO_FPGA1_N
NET "clk_in_p"          LOC = "AH12";            # EXT_CLK_TO_FPGA1_P
NET "rst_n"             LOC = "AH14";            # RESET_N
NET "phy_error"         LOC = "AD19";            # LED 0, D8
NET "error"             LOC = "AE19";            # LED 1, D6
NET "dcm_locked"        LOC = "AE17";            # LED 2, D9
NET "ctrl_ready"        LOC = "AF16";            # LED 3, D7

# Reserve for future expansion
#NET     "AD<13>"        LOC =   "F33" ;         # DDR1_A13
#NET     "CS_n<1>"       LOC =   "AC33" ;        # DDR1_BY2_3_CS_N
#NET     "CK_n<1>"       LOC =   "AE34" ;        # DDR1_CK2_N
#NET     "CK<1>"         LOC =   "AF34" ;        # DDR1_CK2_P
#NET     "DM<2>"         LOC =   "P34" ;         # DDR1_DM_BY2
#NET     "DM<3>"         LOC =   "G32" ;         # DDR1_DM_BY3
#NET     "DQS<2>"        LOC =   "K33" ;         # DDR1_DQS_BY2_P
#NET     "DQS<3>"        LOC =   "J32" ;         # DDR1_DQS_BY3_P
#NET     "DQ<16>"        LOC =   "U31" ;         # DDR1_DQ_BY2_B0
#NET     "DQ<17>"        LOC =   "U32" ;         # DDR1_DQ_BY2_B1
#NET     "DQ<18>"        LOC =   "T34" ;         # DDR1_DQ_BY2_B2
#NET     "DQ<19>"        LOC =   "U33" ;         # DDR1_DQ_BY2_B3
#NET     "DQ<20>"        LOC =   "R32" ;         # DDR1_DQ_BY2_B4
#NET     "DQ<21>"        LOC =   "R33" ;         # DDR1_DQ_BY2_B5
#NET     "DQ<22>"        LOC =   "R34" ;         # DDR1_DQ_BY2_B6
#NET     "DQ<23>"        LOC =   "T33" ;         # DDR1_DQ_BY2_B7
#NET     "DQ<24>"        LOC =   "D34" ;         # DDR1_DQ_BY3_B0
#NET     "DQ<25>"        LOC =   "C34" ;         # DDR1_DQ_BY3_B1
#NET     "DQ<26>"        LOC =   "D32" ;         # DDR1_DQ_BY3_B2
#NET     "DQ<27>"        LOC =   "C32" ;         # DDR1_DQ_BY3_B3
#NET     "DQ<28>"        LOC =   "C33" ;         # DDR1_DQ_BY3_B4
#NET     "DQ<29>"        LOC =   "B33" ;         # DDR1_DQ_BY3_B5
#NET     "DQ<30>"        LOC =   "A33" ;         # DDR1_DQ_BY3_B6
#NET     "DQ<31>"        LOC =   "B32" ;         # DDR1_DQ_BY3_B7

###############################################################################
# I/O Standards
# NOTES:
#  1. Depending on user's application, data and strobe signals may need 
#     to use DCI standard for FPGA-side termination. Consult your friendly 
#     board-designer/IBIS/SPICE-simulator to see if this is necessary. 
###############################################################################