clk_module.vhd

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-------------------------------------------------------------------------------
-- Copyright (c) 2006 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor: Xilinx
-- \   \   \/    Version: 1.1
--  \   \        Filename: CLK_module.vhd
--  /   /        Date Last Modified: 5/10/06
-- /___/   /\    Date Created:
-- \   \  /  \
--  \___\/\___\
-- 
--Device: Virtex-5
--Purpose: Clock generation logic. Instantiates DCM and global clock
--         buffers for CLK0, CLK90. Instantiates IDELAYCTRL (only one IDELAY
--         instantiated - MAP should replicate these as appropriate for user 
--         design; user can also add more IDELAYCTRLs explicitly as required)
--Reference:
--    XAPP851
--Revision History:
--    Rev 1.0 - Internal release. Author: Toshihiko Moriyama. 4/29/06.
--    Rev 1.1 - External release. Added header. Removed second IDELAYCTRL.
--              5/10/06.
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;

entity CLK_module is
Port (
	rst				: in std_logic;
	clk200_in		: in std_logic;
	clk_in			: in std_logic;

	clk0			: out std_logic;
	clk90			: out std_logic;
	locked			: out std_logic
);
end CLK_module;

architecture RTL of CLK_module is

	signal clk200			: std_logic;
	signal clk0_dcm			: std_logic;
	signal clk0_bufg		: std_logic;
	signal clk90_dcm		: std_logic;
	signal locked_dcm		: std_logic;
	signal idlyctl_rdy		: std_logic;
	signal idlyctl_rdy0		: std_logic;

begin

	locked <= idlyctl_rdy and locked_dcm;

	-----------------------------------------------------
	BUFG_REFCLK : BUFG
	PORT MAP (
	O => clk200,
	I => clk200_in
	);

	DLYCTRL0 : IDELAYCTRL
	PORT MAP (
	RDY		=> idlyctl_rdy0,
	REFCLK	=> clk200,
	rst		=> rst
	);

	idlyctl_rdy <= idlyctl_rdy0;

	BUFG_CLK0 : BUFG
	PORT MAP (
	O => clk0_bufg,
	I => clk0_dcm
	);
	clk0 <= clk0_bufg;

	BUFG_CLK90 : BUFG
	PORT MAP (
	O => clk90,
	I => clk90_dcm
	);

	-----------------------------------------------------

	DCM_BASE_inst : DCM_BASE
	generic map (
	CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
					   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
	CLKFX_DIVIDE => 1,   -- Can be any interger from 1 to 32
	CLKFX_MULTIPLY => 2, -- Can be any integer from 2 to 32
	CLKIN_DIVIDE_BY_2 => FALSE,	-- TRUE/FALSE to enable CLKIN divide by two feature
	CLKIN_PERIOD => 5.0,			-- Specify period of input clock in ns from 1.25 to 1000.00
	CLKOUT_PHASE_SHIFT => "NONE",	-- Specify phase shift mode of NONE or FIXED
	CLK_FEEDBACK => "1X",					-- Specify clock feedback of NONE or 1X
	DCM_PERFORMANCE_MODE => "MAX_SPEED",		-- Can be MAX_SPEED or MAX_RANGE
	DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",	-- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
											--   an integer from 0 to 15
	DFS_FREQUENCY_MODE => "HIGH",		-- LOW or HIGH frequency mode for frequency synthesis
	DLL_FREQUENCY_MODE => "HIGH",		-- LOW, HIGH, or HIGH_SER frequency mode for DLL
	DUTY_CYCLE_CORRECTION => TRUE,	-- Duty cycle correction, TRUE or FALSE
	FACTORY_JF => X"F0F0",			-- FACTORY JF Values Suggested to be set
									-- to 16'hC080 for LOW
									-- DLL_FREQUENCY_MODE and to 16'hF0F0
									-- for HIGH DLL_FREQUENCY_MODE
	PHASE_SHIFT => 0,			-- Amount of fixed phase shift from -255 to 1023
	STARTUP_WAIT => FALSE)	-- Delay configuration DONE until DCM LOCK, TRUE/FALSE
	port map (
	CLK0		=> clk0_dcm,	-- 0 degree DCM CLK ouptput
	CLK180		=> open,		-- 180 degree DCM CLK output
	CLK270		=> open,		-- 270 degree DCM CLK output
	CLK2X		=> open,		-- 2X DCM CLK output
	CLK2X180	=> open,		-- 2X, 180 degree DCM CLK out
	CLK90		=> clk90_dcm,	-- 90 degree DCM CLK output
	CLKDV		=> open,		-- Divided DCM CLK out (CLKDV_DIVIDE)
	CLKFX		=> open,		-- DCM CLK synthesis out (M/D)
	CLKFX180	=> open,		-- 180 degree CLK synthesis out
	LOCKED		=> locked_dcm,	-- DCM LOCK status output
	CLKFB		=> clk0_bufg,	-- DCM clock feedback
	CLKIN		=> clk_in,		-- Clock input (from IBUFG, BUFG or DCM)
	RST			=> rst			-- DCM asynchronous reset input
	);


end RTL;