ddr1_controller.vhd

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 if(clk0'event and clk0 = '1') then
   if(rst = '1') then
	ctrl_Wdf_RdEn_r1 <= '0';
   else
	ctrl_Wdf_RdEn_r1 <= ctrl_Wdf_RdEn_r;
   end if;
 end if;
end process;

ctrl_Wdf_RdEn <= ctrl_Wdf_RdEn_r1 when (REGISTERED_VALUE = '1') else
		 ctrl_Wdf_RdEn_r;

process (clk0)
begin
 if(clk0'event and clk0 = '1') then
   if(rst = '1') then
      state <= IDLE;
  else
     state <= next_state;
  end if;
 end if;
end process;

--Main control state machine
process (ACT_r, LMR_PRE_REF_ACT_cmd_r, LMR_r, RD
	 , RD_r, REF_r, WR, WR_r, auto_ref
	 , conflict_detect, conflict_detect_r
	 , conflict_resolved_r, idle_cnt, mrd_count, ras_count, rcd_count
	 , rd_to_wr_count, read_burst_cnt, rfc_count, rp_count
	 , rtp_count, state, wr_to_rd_count, wrburst_cnt
	 , wtp_count,burst_cnt, af_empty_r)
begin

   next_state <= state;
   case state is
	when IDLE =>
	if ((conflict_detect_r = '1' or LMR_PRE_REF_ACT_cmd_r = '1' or auto_ref = '1') and ras_count = "0000") then
	   next_state <= PRECHARGE;
	elsif ((WR_r= '1'  or RD_r= '1') and (ras_count = "0000")) then
	   next_state <= ACTIVE;
	end if;

        when LOAD_MODE_REG_ST  => next_state <= MODE_REGISTER_WAIT;

	when MODE_REGISTER_WAIT =>
        if (mrd_count = '0') then
          next_state <= IDLE;
        else
          next_state <= MODE_REGISTER_WAIT;
        end if;

	when PRECHARGE  => next_state <= PRECHARGE_WAIT;


	when PRECHARGE_WAIT =>
        if (rp_count = "000") then
           if ((auto_ref or REF_r) = '1') then
              next_state <= AUTO_REFRESH;
	   elsif (LMR_r = '1') then
              next_state <= LOAD_MODE_REG_ST;
	   elsif ((conflict_detect_r or ACT_r) = '1') then
              next_state <= ACTIVE;
           else
              next_state <= IDLE;
           end if;
        else
           next_state <= PRECHARGE_WAIT;
        end if;

	when AUTO_REFRESH => next_state <= AUTO_REFRESH_WAIT;

	when AUTO_REFRESH_WAIT =>
        if ( (rfc_count = "00001") and (conflict_detect_r = '1') ) then
           next_state <= ACTIVE;
        elsif (rfc_count = "00001") then
           next_state <= IDLE;
        else
           next_state <= AUTO_REFRESH_WAIT;
        end if;

	when ACTIVE  => next_state <= ACTIVE_WAIT;


	when ACTIVE_WAIT  =>
        if (rcd_count = "000") then
	   if(WR = '1') then
             next_state <= FIRST_WRITE;
           elsif (RD = '1') then
             next_state <= FIRST_READ;
           else
             next_state <= IDLE;
	   end if;
	else
	  next_state <= ACTIVE_WAIT;
	end if;

	when FIRST_WRITE  =>
	      if((((conflict_detect = '1') and (conflict_resolved_r ='0')) or (auto_ref = '1')) or RD = '1') then
		 next_state <= WRITE_WAIT;
	      elsif((burst_cnt = "001") and (WR = '1')) then
		  next_state <= BURST_WRITE;
	      else
		  next_state <= WRITE_WAIT;
	      end if;

	when BURST_WRITE =>
	      if((((conflict_detect = '1') and (conflict_resolved_r = '0')) or (auto_ref = '1')) or (RD = '1')) then
		 next_state <= WRITE_WAIT;
	      elsif((burst_cnt = "001") and (WR = '1')) then
		  next_state <= BURST_WRITE;
	      else
		  next_state <= WRITE_WAIT;
	      end if;

	when WRITE_WAIT =>
        if (((conflict_detect = '1') and (conflict_resolved_r = '0')) or (auto_ref = '1')) then
	   if ((wtp_count = "0000") and (ras_count = "0000")) then
             next_state <= PRECHARGE;
           else
             next_state <= WRITE_WAIT;
	   end if;
        elsif (RD = '1') then
           next_state <= WRITE_READ;
        elsif ((WR ='1') and (wrburst_cnt = "010")) then
           next_state <= BURST_WRITE;
        elsif (idle_cnt = "0000") then
           next_state <= PRECHARGE;
	else
           next_state <= WRITE_WAIT;
	end if;

	when WRITE_READ =>
        if (wr_to_rd_count = "0000") then
           next_state <= FIRST_READ;
        else
           next_state <= WRITE_READ;
        end if;

	when FIRST_READ   =>
	      if((((conflict_detect = '1') and (conflict_resolved_r = '0')) or (auto_ref = '1')) or (WR = '1')) then
		 next_state <= READ_WAIT;
	      elsif((burst_cnt = "001") and (RD = '1')) then
		  next_state <= BURST_READ;
	      else
		  next_state <= READ_WAIT;
	      end if;

	when BURST_READ  =>
	      if((((conflict_detect = '1') and (conflict_resolved_r = '0'))or (auto_ref = '1')) or (WR = '1')) then
		 next_state <= READ_WAIT;
	      elsif((burst_cnt = "001") and (RD = '1')) then
		  next_state <= BURST_READ;
	      else
		  next_state <= READ_WAIT;
	      end if;

	when READ_WAIT  =>
        if (((conflict_detect = '1') and (conflict_resolved_r = '0')) or (auto_ref = '1')) then
           if(rtp_count = "0000" and ras_count = "0000") then
             next_state <= PRECHARGE;
           else
             next_state <= READ_WAIT;
	   end if;
        elsif (WR = '1') then
           next_state <= READ_WRITE;
        elsif ((RD = '1') and (read_burst_cnt <= "010")) then
	   if(af_empty_r = '1') then
	     next_state <= FIRST_READ;
	   else
             next_state <= BURST_READ;
	   end if;
        elsif (idle_cnt = "0000") then
           next_state <= PRECHARGE;
        else
           next_state <= READ_WAIT;
        end if;


	when READ_WRITE  =>
        if (rd_to_wr_count = "0000") then
           next_state <= FIRST_WRITE;
        else
           next_state <= READ_WRITE;
        end if;

	when others => next_state <= IDLE;

   end case;
end process;

--register command outputs
process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
      state_r2 <= "00000";
      state_r3 <= "00000";
   else
      state_r2 <= state;
      state_r3 <= state_r2;
  end if;
 end if;
end process;

-- commands to the memory
process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
      ddr_ras_r <= '1';
   elsif ((state = LOAD_MODE_REG_ST) or (state = PRECHARGE) or (state = ACTIVE) or (state = AUTO_REFRESH)) then
      ddr_ras_r <= '0';
   else ddr_ras_r <= '1';
  end if;
 end if;
end process;

-- commands to the memory
process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
      ddr_cas_r <= '1';
   elsif ((state = LOAD_MODE_REG_ST)  or (read_write_state = '1') or (state = AUTO_REFRESH)) then
      ddr_cas_r <= '0';
   elsif ((state = ACTIVE_WAIT)) then
      ddr_cas_r <= '1';
   else
      ddr_cas_r <= '1';
  end if;
 end if;
end process;

-- commands to the memory
process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
      ddr_we_r <= '1';
   elsif ((state = LOAD_MODE_REG_ST) or (state = PRECHARGE) or (write_state = '1')) then
      ddr_we_r <= '0';
   else ddr_we_r <= '1';
  end if;
 end if;
end process;

--register commands to the memory
process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
      ddr_ras_r2 <= '1';
      ddr_cas_r2 <= '1';
      ddr_we_r2 <= '1';
   else
      ddr_ras_r2  <= ddr_ras_r;
      ddr_cas_r2  <= ddr_cas_r;
      ddr_we_r2   <= ddr_we_r;
  end if;
 end if;
end process;

--register commands to the memory
process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if (rst = '1') then
	ddr_ras_r3 <= '1';
	ddr_cas_r3 <= '1';
	ddr_we_r3  <= '1';
   else
	ddr_ras_r3  <= ddr_ras_r2;
	ddr_cas_r3  <= ddr_cas_r2;
	ddr_we_r3   <= ddr_we_r2;
  end if;
 end if;
end process;

process (clk0)
begin
 if(clk0'event and clk0 = '1') then
   if(rst = '1') then
       row_addr_r(row_address-1 downto 0) <= (others => '0');
  else
       row_addr_r(row_address-1 downto 0) <= af_addr((row_address + col_ap_width)-1 downto col_ap_width);
  end if;
 end if;
end process;

-- chip enable generation logic
process(clk0)
 begin
  if (clk0='1' and clk0'event) then
      if (rst = '1')  then
          ddr_cs_r((no_of_cs-1) downto 0) <=  (others => '0');
      else
          if (af_addr_r((chip_address + bank_address +row_address + (col_ap_width-1)) downto (bank_address + row_address + col_ap_width)) =
	      cs_h0((chip_address - 1) downto 0)) then
                       ddr_cs_r((no_of_cs-1) downto  0) <=  cs_hE((no_of_cs-1) downto  0);
          elsif (af_addr_r((chip_address + bank_address + row_address + (col_ap_width-1)) downto (bank_address +row_address + col_ap_width)) =
		 cs_h1((chip_address - 1) downto 0))   then
                     ddr_cs_r((no_of_cs-1) downto 0) <=  cs_hD((no_of_cs-1) downto  0);
          elsif (af_addr_r((chip_address + bank_address +row_address + (col_ap_width-1)) downto (bank_address + row_address + col_ap_width)) =
		  cs_h2((chip_address - 1) downto 0)) then
                     ddr_cs_r((no_of_cs-1) downto 0) <= cs_hB((no_of_cs-1) downto  0);
         elsif (af_addr_r((chip_address + bank_address +row_address + (col_ap_width-1)) downto (bank_address + row_address + col_ap_width)) =
		    cs_h3((chip_address - 1) downto 0)) then
		         ddr_cs_r((no_of_cs-1) downto 0) <=  cs_h7((no_of_cs-1) downto  0);
         else
                     ddr_cs_r((no_of_cs-1) downto 0) <=  cs_hF((no_of_cs-1) downto  0);
         end if;
      end if;
  end if;
end process;

process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
      ddr_address_r1 <= (others => '0');
   elsif ((state_r2 = ACTIVE)) then
      ddr_address_r1 <= row_addr_r;
   elsif (read_write_state_r2 = '1') then
      ddr_address_r1 <= af_addr_r(row_address-1 downto 0) and add_const4((row_address-1) downto 0); -- Auto Precharge option is disabled
   elsif (state_r2 = PRECHARGE) then
      if(PRE_r = '1') then
        ddr_address_r1 <= af_addr_r(row_address-1 downto 0);
      else
        ddr_address_r1 <= add_const1((row_address-1) downto 0);--X"0400";
      end if;
   elsif (state_r2 = LOAD_MODE_REG_ST)then
      ddr_address_r1 <= af_addr_r(row_address-1 downto 0);
   else
      ddr_address_r1 <= add_const3((row_address-1) downto 0);--X"0000";
  end if;
 end if;
end process;

process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
      ddr_ba_r1(bank_address-1 downto 0) <= (others => '0');
   elsif ((state_r2 = ACTIVE) or (state_r2 = LOAD_MODE_REG_ST) or ((state_r2 = PRECHARGE) and PRE_r = '1')) then
      ddr_ba_r1(bank_address-1 downto 0) <= af_addr((bank_address+row_address + col_ap_width)-1 downto (col_ap_width + row_address));
   else
      ddr_ba_r1(bank_address-1 downto 0) <= ddr_ba_r1(bank_address-1 downto 0);
  end if;
 end if;
end process;

process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
      ddr_cs_r1 <= (others => '0');
    elsif (state_r3 = auto_refresh ) then
      ddr_cs_r1 <= (others => '0');
    elsif ((state_r3 = active ) or (state_r3 = load_mode_reg_st) or (state_r3 = precharge_wait )) then
      ddr_cs_r1 <= ddr_cs_r;
    else
      ddr_cs_r1 <= ddr_cs_r1;
    end if;
  end if;
end process;

process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
      conflict_resolved_r <= '0';
   else
      if ((state = PRECHARGE_WAIT)  and (conflict_detect_r= '1')) then
        conflict_resolved_r  <= '1';
      elsif(af_rden = '1') then
        conflict_resolved_r  <= '0';
      end if;
  end if;
 end if;
end process;

process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
       ddr_cke_r<= '0';
   else
      if(done_200us = '1') then
	ddr_cke_r<= '1';
      end if;
   end if;
 end if;
end process;

 ctrl_ddr_address(row_address-1 downto 0)  <= ddr_address_r1(row_address-1 downto 0);
 ctrl_ddr_ba (bank_address-1 downto 0)     <= ddr_ba_r1(bank_address-1 downto 0);
 ctrl_ddr_ras_L <= ddr_ras_r2;
 ctrl_ddr_cas_L <= ddr_cas_r2;
 ctrl_ddr_we_L  <= ddr_we_r2;
 ctrl_ddr_cs_L <= (others => '0');
 ctrl_ddr_cke  <= ddr_cke_r;

end arch;