ddr1_controller.vhd

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-- rtp count - read to precharge
process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
       rtp_count(3 downto 0) <= "0000";
   elsif (read_state = '1') then
       rtp_count(2 downto 0) <= trtp_count_value ;
   elsif (rtp_count(3 downto 1) = "000") then
       if (rtp_count(0) /= '0') then
              rtp_count(0) <= '0';
       end if;
   else
       rtp_count(3 downto 0) <= rtp_count(3 downto 0) - 1;
  end if;
 end if;
end process;

-- WL+BL/2+TWR
-- wtp count - write to precharge
process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
       wtp_count(3 downto 0) <= "0000";
   elsif (write_state = '1') then
       wtp_count(2 downto 0) <= twr_count_value  ;
   elsif (wtp_count(3 downto 1) = "000") then
       if (wtp_count(0) /= '0') then
              wtp_count(0) <= '0';
       end if;
   else
       wtp_count(3 downto 0) <= wtp_count(3 downto 0) - 1;
  end if;
 end if;
end process;

-- write to read counter
process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
       wr_to_rd_count(3 downto 0) <= "0000";
   elsif (write_state = '1') then
       wr_to_rd_count(2 downto 0) <= twtr_count_value;
   elsif (wr_to_rd_count(3 downto 0) /= "0000") then
       wr_to_rd_count(3 downto 0) <= wr_to_rd_count(3 downto 0) - 1;
   else
     wr_to_rd_count(3 downto 0) <= "0000";
  end if;
 end if;
end process;

-- read to write counter
process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
      rd_to_wr_count(3 downto 0) <= "0000";
   elsif (read_state = '1') then
      -- MODIFIED, RCHIU, 06/28/06
      -- Fixed CL=2.5 read-write spacing bug
      rd_to_wr_count(3 downto 0) <=  registered + burst_cnt + rd_to_wr_cas_delay;
--      rd_to_wr_count(3 downto 0) <=  registered + burst_cnt + CAS_LATENCY_VALUE(0);
   elsif (rd_to_wr_count(3 downto 0) /= "0000") then
      rd_to_wr_count(3 downto 0) <= rd_to_wr_count(3 downto 0) - 1;
   else
     rd_to_wr_count(3 downto 0) <= "0000";
  end if;
 end if;
end process;

-- auto refresh interval counter in refresh_clk domain
process (refresh_clk)
begin
 if(refresh_clk'event and refresh_clk = '1') then
   if(rst = '1') then
      refi_count <= (others => '0');
   elsif (refi_count = max_ref_cnt ) then
      refi_count <= (others => '0');
   else
      refi_count <= refi_count + 1;
  end if;
 end if;
end process;

 ref_flag <= '1' when ((refi_count = max_ref_cnt) and (done_200us = '1') ) else
	    '0';

--200us counter for cke
-- Commented for later use
--process (refresh_clk)
--begin
-- if(refresh_clk'event and refresh_clk = '1') then
--  if (rst = '1') then
--    cke_200us_cnt <= "11011";
--  elsif (refi_count(max_ref_width-1  downto  0) =  max_ref_cnt) then
--    cke_200us_cnt  <=  cke_200us_cnt - 1;
--  else
--    cke_200us_cnt  <= cke_200us_cnt;
--  end if;
-- end if;
--end process;

-- refresh detect in 266 MHz clock
process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
      ref_flag_266   <= '0';
      ref_flag_266_r <= '0';
      done_200us <= '0';
   else
      ref_flag_266   <= ref_flag;
      ref_flag_266_r <= ref_flag_266;
--      if (done_200us = '0' and (cke_200us_cnt = "00000")) then --comment should be removed later
	done_200us <= '1';
--      end if;
  end if;
 end if;
end process;

--refresh flag detect
--auto_ref high indicates auto_refresh requirement
--auto_ref is held high until auto refresh command is issued.
process(clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
       auto_ref <= '0';
    elsif (ref_flag_266 = '1' and ref_flag_266_r = '0') then
       auto_ref <= '1';
    elsif (state = AUTO_REFRESH) then
       auto_ref <= '0';
    else
       auto_ref <= auto_ref;
  end if;
 end if;
end process;


burst_cnt           <= "0010" when (BURST_LENGTH_VALUE = "010") else
                       "0100" when (BURST_LENGTH_VALUE = "011") else
		       "0001";
burst_cnt_by2	     <= "001" when (BURST_LENGTH_VALUE = "010") else
                       "010" when (BURST_LENGTH_VALUE = "011") else
		       "000";

-- write burst count
process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
       wrburst_cnt(2 downto 0) <= "000";
   elsif (write_state = '1') then
       wrburst_cnt(2 downto 0) <= burst_cnt(2 downto 0);
   elsif (wrburst_cnt(2 downto 0) /= "000") then
       wrburst_cnt(2 downto 0) <= wrburst_cnt(2 downto 0) - 1;
   else wrburst_cnt(2 downto 0) <= "000";
  end if;
 end if;
end process;

-- read burst count for state machine
process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
       read_burst_cnt(2 downto 0) <= "000";
   elsif (read_state = '1') then
       read_burst_cnt(2 downto 0) <= burst_cnt(2 downto 0);
   elsif (read_burst_cnt(2 downto 0) /= "000") then
       read_burst_cnt(2 downto 0) <= read_burst_cnt(2 downto 0) - 1;
   else read_burst_cnt(2 downto 0) <= "000";
  end if;
 end if;
end process;

-- count to generate write enable to the data path
process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
       ctrl_WrEn_cnt(2 downto 0) <= "000";
   elsif (wdf_rden_r = '1') then
       ctrl_WrEn_cnt(2 downto 0) <= burst_cnt(2 downto 0);
   elsif (ctrl_WrEn_cnt(2 downto 0) /= "000") then
       ctrl_WrEn_cnt(2 downto 0) <= ctrl_WrEn_cnt(2 downto 0) -1;
   else
       ctrl_WrEn_cnt(2 downto 0) <= "000";
  end if;
 end if;
end process;

--write enable to data path
process (ctrl_WrEn_cnt)
begin
     if (ctrl_WrEn_cnt(2 downto 0) /= "000") then
        ctrl_WrEn_r <= '1';
     else
        ctrl_WrEn_r <= '0';
     end if;
end process;

process(clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
	ctrl_WrEn_r1 <= '0';
    else
	ctrl_WrEn_r1 <= ctrl_WrEn_r;
    end if;
 end if;
end process;

ctrl_WrEn <= ctrl_WrEn_r1 when (REGISTERED_VALUE = '1') else
	     ctrl_WrEn_r;


-- DQS reset to data path
process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
      ctrl_Dqs_Rst_r <= '0';
   elsif (first_write_state = '1') then
      ctrl_Dqs_Rst_r <= '1';
   else
      ctrl_Dqs_Rst_r <= '0';
  end if;
 end if;
end process;

process(clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
	ctrl_Dqs_Rst_r1 <= '0';
    else
	ctrl_Dqs_Rst_r1 <= ctrl_Dqs_Rst_r;
    end if;
 end if;
end process;

ctrl_Dqs_Rst <= ctrl_Dqs_Rst_r1 when (REGISTERED_VALUE = '1') else
		ctrl_Dqs_Rst_r;

-- DQS enable to data path
process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
      ctrl_Dqs_En_r <= '0';
   elsif ((write_state = '1') or (wrburst_cnt /= "000")) then
      ctrl_Dqs_En_r <= '1';
   else
      ctrl_Dqs_En_r <= '0';
  end if;
 end if;
end process;

process(clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
	ctrl_Dqs_En_r1 <= '0';
    else
	ctrl_Dqs_En_r1 <= ctrl_Dqs_En_r;
    end if;
 end if;
end process;

ctrl_Dqs_En <= ctrl_Dqs_En_r1 when (REGISTERED_VALUE = '1') else
	       ctrl_Dqs_En_r;


-- read_wait/write_wait to idle count
-- the state machine waits for 15 clock cycles in the write wait state for any wr/rd commands
-- to be issued. If no commands are issued in 15 clock cycles, the statemachine issues
--  enters the idle state and stays in the idle state until an auto refresh is required.

process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
       idle_cnt(3 downto 0) <= "0000";
   elsif (read_write_state = '1') then
       idle_cnt(3 downto 0) <= "1111" ;
   elsif (idle_cnt(3 downto 0) /= "0000") then
       idle_cnt(3 downto 0) <= idle_cnt(3 downto 0) - 1;
   else idle_cnt(3 downto 0) <= "0000";
  end if;
 end if;
end process;

process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if(rst = '1') then
       cas_check_count(3 downto 0) <= "0000";
   elsif (first_read_state_r2 = '1')  then
          cas_check_count(3 downto 0) <= (CAS_LATENCY_VALUE - 1);
   elsif (cas_check_count(3 downto 0) /= "0000") then
       cas_check_count(3 downto 0) <= cas_check_count(3 downto 0) - 1;
   else
     cas_check_count(3 downto 0) <= "0000";
  end if;
 end if;
end process;

process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if (rst = '1') then
      rdburst_cnt(2 downto 0) <= "000";
      ctrl_RdEn_r <= '0';
   elsif ((cas_check_count = "0001") and (burst_read_state_r3 = '0')) then
      rdburst_cnt(2 downto 0) <= burst_cnt(2 downto 0);
      ctrl_RdEn_r <= '1';
   elsif(burst_read_state_r3 = '1') then
      if(burst_cnt = "0100") then
	rdburst_cnt(2 downto 0) <= CAS_LATENCY_VALUE(2 downto 0) + burst_cnt_by2;
      elsif (burst_cnt = "010") then
        rdburst_cnt(2 downto 0) <= CAS_LATENCY_VALUE(2 downto 0);
      else
	rdburst_cnt(2 downto 0) <= CAS_LATENCY_VALUE(2 downto 0) - burst_cnt(2 downto 0);
      end if;
      ctrl_RdEn_r <= '1';
   elsif (rdburst_cnt(2 downto 0) /= "000") then
      rdburst_cnt(2 downto 0) <= rdburst_cnt(2 downto 0) - '1';
      if(rdburst_cnt = "001") then
        ctrl_RdEn_r <= '0';
      end if;
   else
     rdburst_cnt(2 downto 0) <= "000";
  end if;
 end if;
end process;

process(clk0)
begin
 if(clk0'event and clk0 = '1') then
    if (rst = '1') then
	ctrl_RdEn_r1 <= '0';
    else
	ctrl_RdEn_r1 <= ctrl_RdEn_r;
    end if;
 end if;
end process;

ctrl_RdEn <= ctrl_RdEn_r1 when (REGISTERED_VALUE = '1') else
	     ctrl_RdEn_r;

-- write address FIFO read enable signals

af_rden <= '1' when ((read_write_state = '1') or ((state = MODE_REGISTER_WAIT) and LMR_r = '1' and (mrd_count = '0')) or
                     ((state = PRECHARGE )and PRE_r = '1') or ((state = AUTO_REFRESH) and REF_r = '1')
                     or ((state = ACTIVE )and ACT_r = '1')) else '0';

-- write data fifo read enable
process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if (rst = '1')  then
       wdf_rden_r  <= '0';
   elsif (write_state = '1') then -- place holder for burst_write
       wdf_rden_r  <= '1';
   else
     wdf_rden_r  <= '0';
  end if;
 end if;
end process;

process (clk0)
begin
 if(clk0'event and clk0 = '1') then
    if (rst = '1') then
       wdf_rden_r2 <= '0';
       wdf_rden_r3 <= '0';
       wdf_rden_r4 <= '0';
   else
       wdf_rden_r2 <= wdf_rden_r;
       wdf_rden_r3 <= wdf_rden_r2;
       wdf_rden_r4 <= wdf_rden_r3;
  end if;
 end if;
end process;

-- Read enable to the data fifo

process (burst_cnt, wdf_rden_r, wdf_rden_r2, wdf_rden_r3, wdf_rden_r4)
begin
   if (burst_cnt = "001") then
       ctrl_Wdf_RdEn_r<= (wdf_rden_r ) ;
   elsif (burst_cnt = "010") then
       ctrl_Wdf_RdEn_r<= (wdf_rden_r or wdf_rden_r2) ;
   elsif (burst_cnt = "100") then
       ctrl_Wdf_RdEn_r<= (wdf_rden_r or wdf_rden_r2 or wdf_rden_r3 or wdf_rden_r4) ;
   else
       ctrl_Wdf_RdEn_r<= '0';
   end if;
end process;

process (clk0)
begin